公开(公告)号：US20120243337A1

公开(公告)日：2012-09-27

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US08503229B2

公开(公告)日：2013-08-06

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/94 ,  H01L21/00 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US20120228691A1

公开(公告)日：2012-09-13

申请号：US13072130

申请日：2011-03-25

申请人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

发明人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66825 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/40114 ,  H01L29/7881

摘要： Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有PN浮动栅极的非易失性存储元件。 浮置栅极可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有N +区域。 在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保留。 在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 也可以有效地擦除非易失性存储元件。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US08853763B2

公开(公告)日：2014-10-07

申请号：US13607375

申请日：2012-09-07

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20120326220A1

公开(公告)日：2012-12-27

申请号：US13607375

申请日：2012-09-07

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/78

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US08288293B2

公开(公告)日：2012-10-16

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L21/469

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20100270608A1

公开(公告)日：2010-10-28

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/76

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US07876618B2

公开(公告)日：2011-01-25

申请号：US12409020

申请日：2009-03-23

申请人： Sanghyun Lee ,  Masaaki Higashitani ,  Shinji Sato ,  Chih-Ming Wang

发明人： Sanghyun Lee ,  Masaaki Higashitani ,  Shinji Sato ,  Chih-Ming Wang

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.

摘要翻译： 在编程和感测操作期间具有减小的漏电流的存储器件，以及用于操作这种存储器件的方法。 在非易失性存储器件中，当所选择的块经历程序或读取操作，并且位线由块共享时，在NAND串的漏极选择栅极处的电流泄漏可能发生在未选择的块中。 在其中为两个块提供公共传输栅极驱动器的一种方法中，漏极选择栅极以最佳电平进行预充电，这使泄漏最小化，随后浮动，同时将程序或读取电压施加到所选择的字线 在所选的块中。 在另一种方法中，为未选择的块提供单独的传输栅极驱动器，使得即使在所选择的块中施加编程或读取电压，也可以在未选择的块中驱动最佳选择栅极电压。

公开(公告)号：US20100238729A1

公开(公告)日：2010-09-23

申请号：US12409020

申请日：2009-03-23

申请人： Sanghyun Lee ,  Masaaki Higashitani ,  Shinji Sato ,  Chih-Ming Wang

发明人： Sanghyun Lee ,  Masaaki Higashitani ,  Shinji Sato ,  Chih-Ming Wang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.

摘要翻译： 在编程和感测操作期间具有减小的漏电流的存储器件，以及用于操作这种存储器件的方法。 在非易失性存储器件中，当所选择的块经历程序或读取操作，并且位线由块共享时，在NAND串的漏极选择栅极处的电流泄漏可能发生在未选择的块中。 在其中为两个块提供公共传输栅极驱动器的一种方法中，漏极选择栅极以最佳电平进行预充电，这使泄漏最小化，随后浮动，同时将程序或读取电压施加到所选择的字线 在所选的块中。 在另一种方法中，为未选择的块提供单独的传输栅极驱动器，使得即使在所选择的块中施加编程或读取电压，也可以在未选择的块中驱动最佳选择栅极电压。

公开(公告)号：US08810883B2

公开(公告)日：2014-08-19

申请号：US13559479

申请日：2012-07-26

申请人： Sanghyun Lee ,  Yungkyung Park ,  Dohyoung Kwon ,  Gichang Park ,  Jongseo Lee ,  Andrea Giraldo ,  Nicolas Bergeron

发明人： Sanghyun Lee ,  Yungkyung Park ,  Dohyoung Kwon ,  Gichang Park ,  Jongseo Lee ,  Andrea Giraldo ,  Nicolas Bergeron

IPC分类号： G02B26/02 ,  G02B26/00 ,  G09G3/34

CPC分类号： G09G3/348 ,  G02B5/201 ,  G02B26/005 ,  G02B27/0018 ,  Y10T29/49117

摘要： An electrowetting display apparatus includes a first substrate including a first electrode that receives a gray-scale voltage and a second electrode insulated from the first electrode and receiving a reference voltage, a second substrate, a fluid layer, and a color filter. The color filter has a first thickness in an area corresponding to the first electrode and a second thickness in an area corresponding to the second electrode, and the first thickness is larger than the second thickness. Accordingly, a cell gap of the electrowetting display apparatus is reduced, and color reproducibility of the electrowetting display apparatus is improved without sacrificing brightness.

摘要翻译： 电润湿显示装置包括：第一基板，包括接收灰度电压的第一电极和与第一电极绝缘并接收参考电压的第二电极，第二基板，流体层和滤色器。 滤色器在对应于第一电极的区域中具有第一厚度，并且在与第二电极对应的区域中具有第二厚度，并且第一厚度大于第二厚度。 因此，电润湿显示装置的单元间隙减小，并且电泳润湿显示装置的颜色再现性在不牺牲亮度的情况下得到改善。