公开(公告)号：US08138807B2

公开(公告)日：2012-03-20

申请号：US12388755

申请日：2009-02-19

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： H03L7/00

CPC分类号： H03K3/356139 ,  G06F1/24 ,  H03K17/223

摘要： When a low supply potential has risen while a high supply potential has not risen, a logical value “0” is output as an output signal by applying a ground potential to an input terminal of a latch circuit through a capacitor. On the other hand, when the high supply potential has risen while the low supply potential has not risen, a logical value “0” is output as an output signal by converting the high supply potential into the ground potential by the level shifter. If both the low supply potential and the high supply potential have risen, the logical value “1” is output as an output signal by converting the ground potential into the high supply potential by the level shifter.

摘要翻译： 当低电源电位升高而高电源电位尚未升高时，通过电容器将锁存电路的输入端施加接地电位作为输出信号输出逻辑值“0”。 另一方面，当低供电电位未上升时，当高供电电位上升时，通过电平移位器将高电源电位转换为地电位，输出逻辑值“0”作为输出信号。 如果低电源电位和高电源电位都升高，则通过电平移位器将地电位转换为高电源电位来输出逻辑值“1”作为输出信号。

公开(公告)号：US20100321065A1

公开(公告)日：2010-12-23

申请号：US12703924

申请日：2010-02-11

申请人： Masaharu Wada ,  Takehiko Hojo

发明人： Masaharu Wada ,  Takehiko Hojo

IPC分类号： H03K19/00 ,  H03K19/20

CPC分类号： H03K5/1504 ,  G11C19/00 ,  G11C19/28 ,  H03K5/133 ,  H03K19/00384 ,  H03K2005/00136 ,  H03M1/502

摘要： A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.

摘要翻译： 半导体集成电路包括多路复用器，信号发生电路，控制电路，m个反相器，n个双输入NOR电路和级联的n个双移位寄存器。 控制电路在提供时钟信号的正常操作中产生处于禁止状态的控制信号。 控制电路在不提供时钟信号的情况下，在提供较高的电压源电压的正常以外的操作中产生使能状态的控制信号。 多路复用器接收时钟信号和从信号发生电路输出的低频信号。 在接收到处于禁用状态的控制信号时，多路复用器将时钟信号提供给逆变器的序列，并且在使能状态下接收到控制信号时，将低频信号提供给逆变器的序列。

公开(公告)号：US20100264888A1

公开(公告)日：2010-10-21

申请号：US12648866

申请日：2009-12-29

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/59

CPC分类号： G05F1/59

摘要： A DC/DC converter includes a first regulator supplied with a first reference potential, the first regulator outputting an output potential from an output terminal thereof, the first regulator controlling the output potential so as to be equal to the first reference potential; a second regulator supplied with a second reference potential, the second reference potential being lower than the first reference potential, an output terminal of the second regulator being connected to the output terminal of the first regulator, the second regulator controlling the output potential so as to be equal to the second reference potential; and a first comparator which compares a third reference potential and the output potential, the third reference potential being a potential between the first reference potential and the second reference potential, the first comparator putting the second regulator into an operating state under a first condition in which the output potential is lower than the third reference potential, the first comparator putting the second regulator into a stopped state under a second condition in which the output potential is higher than the third reference potential.

摘要翻译： DC / DC转换器包括提供有第一参考电位的第一调节器，第一调节器从其输出端输出输出电位，第一调节器将输出电位控制为等于第一参考电位; 提供有第二参考电位的第二调节器，第二参考电位低于第一参考电位，第二调节器的输出端连接到第一调节器的输出端，第二调节器控制输出电位，以便 等于第二参考电位; 以及第一比较器，其比较第三参考电位和所述输出电位，所述第三参考电位是所述第一参考电位和所述第二参考电位之间的电位，所述第一比较器将所述第二调节器置于第一条件下的操作状态，其中 所述输出电位低于所述第三参考电位，所述第一比较器在所述输出电位高于所述第三参考电位的第二条件下将所述第二调节器置于停止状态。

公开(公告)号：US20090040809A1

公开(公告)日：2009-02-12

申请号：US12181926

申请日：2008-07-29

申请人： Masaharu Wada ,  Takehiko Hojo

发明人： Masaharu Wada ,  Takehiko Hojo

IPC分类号： G11C11/416 ,  G11C11/00

CPC分类号： G11C17/16 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069

摘要： A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through the first contact, the wiring, and the second contact, and changing resistance values of the first contact to write information; and a read switching circuit controlling current for reading information that flows through the first contact, the wiring, and the third contact.

摘要翻译： 存储装置包括：包括具有第一导电性的第一导体的布线; 以及第一，第二和第三触点，每个包括具有第二导电性的第二导体并接触布线。 存储装置还包括：写入切换电路，控制用于写入流经第一触点，布线和第二触点的信息的电流，以及改变第一触点的电阻值以写入信息; 以及读取切换电路，控制用于读取流过第一触点，布线和第三触点的信息的电流。

公开(公告)号：US07315196B2

公开(公告)日：2008-01-01

申请号：US11004864

申请日：2004-12-07

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/10 ,  H03K3/01

CPC分类号： H02M3/073 ,  H02M2003/078

摘要： A pump circuit includes first and second transistors connected between an input terminal and an output terminal, and a capacitor which is connected at its one end to the connection node of the first and second transistors. The pump circuit is responsive to control signals applied to the gate electrodes of the first and second transistors and another end of the capacitor to output from the output terminal a second voltage which is approximately equal to a first voltage applied to the input terminal. A back-gate voltage generating circuit which produces a third voltage which is less than the lower one of the first and second voltages. The third voltage is applied to at least the back gate of the second transistor which outputs the second voltage.

摘要翻译： 泵电路包括连接在输入端子和输出端子之间的第一和第二晶体管，以及在其一端连接到第一和第二晶体管的连接节点的电容器。 泵电路响应于施加到第一和第二晶体管的栅电极的控制信号，电容器的另一端从输出端输出大致等于施加到输入端的第一电压的第二电压。 一种产生低于第一和第二电压中的较低电压的第三电压的背栅极电压产生电路。 第三电压被施加到输出第二电压的第二晶体管的至少后栅极。

公开(公告)号：US09707663B2

公开(公告)日：2017-07-18

申请号：US14001791

申请日：2012-01-30

申请人： Kuniyasu Shiro ,  Masaharu Wada ,  Hiroyasu Kato ,  Hajime Nishimura ,  Satoshi Yanagisawa ,  Yukihiro Matsuzaki

发明人： Kuniyasu Shiro ,  Masaharu Wada ,  Hiroyasu Kato ,  Hajime Nishimura ,  Satoshi Yanagisawa ,  Yukihiro Matsuzaki

IPC分类号： D06N3/00 ,  D06N3/14 ,  B24B37/24

CPC分类号： B24B37/24 ,  D06N3/0004 ,  D06N3/14 ,  D06N2205/24

摘要： A polishing pad is provided with a compression elastic modulus of 0.17 MPa or more and 0.32 MPa or less produced by preparing a nonwoven fabric formed of bundles of ultrafine fibers with an average monofilament diameter of 3.0 μm or more and 8.0 μm or less, preparing a polishing pad base by impregnating the nonwoven fabric with a polyurethane based elastomer in an amount of 20 mass % or more and 50 mass % or less relative to the mass of the polishing pad base, and laminating the polishing pad base with a porous polyurethane layer containing wet-solidified polyurethane as primary component which has openings with an average opening diameter of 10 μm or more and 90 μm or less in its surface to serve as polishing surface layer.

公开(公告)号：US08837240B2

公开(公告)日：2014-09-16

申请号：US13618976

申请日：2012-09-14

申请人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

发明人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/76 ,  G11C29/78 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2229/743 ,  G11C2229/746

摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

摘要翻译： 第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。 第一缺陷地址数据存储电路输出表示存储单元阵列中的有缺陷的存储单元的地址的第一缺陷地址数据。 第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。 第二缺陷地址数据存储电路输出指示存储单元阵列中缺陷存储单元地址的第二缺陷地址数据。 第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

公开(公告)号：US08791750B2

公开(公告)日：2014-07-29

申请号：US13022888

申请日：2011-02-08

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/10

CPC分类号： G05F3/242 ,  G05F3/30 ,  Y10T307/406

摘要： A constant voltage constant current generation circuit includes a first transistor, a first resistor connected between the first terminal and a second potential, a first diode connected in series with the first resistor, and a first operational amplifier which outputs a first control signal to a control terminal of the first transistor. The constant voltage constant current generation circuit includes a current output circuit which outputs a constant current from a current output terminal according to the first control signal, a second transistor through which a second current flows, the second current obtained by mirroring a first current flowing through the first transistor, a second resistor connected between the voltage output terminal and the second potential. The constant voltage constant current generation circuit includes a current source which outputs a current to the voltage output terminal, and which has negative current characteristics with respect to a temperature change, and a reference voltage output circuit which outputs the reference voltage from a reference voltage terminal.

摘要翻译： 恒压恒流产生电路包括：第一晶体管，连接在第一端子和第二电位之间的第一电阻器，与第一电阻器串联连接的第一二极管;以及第一运算放大器，其将第一控制信号输出到控制器 端子的第一晶体管。 恒压恒定电流产生电路包括电流输出电路，该电流输出电路根据第一控制信号输出来自电流输出端的恒定电流，第二电流流过的第二晶体管，通过镜像流过第一电流而获得的第二电流 第一晶体管，连接在电压输出端和第二电位之间的第二电阻。 恒压恒定电流产生电路包括：电流源，其向电压输出端子输出电流，并且相对于温度变化具有负电流特性;以及参考电压输出电路，其从参考电压端子输出参考电压 。

公开(公告)号：US20130077420A1

公开(公告)日：2013-03-28

申请号：US13618976

申请日：2012-09-14

申请人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

发明人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

IPC分类号： G11C29/00

CPC分类号： G11C29/76 ,  G11C29/78 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2229/743 ,  G11C2229/746

摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

摘要翻译： 第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。 第一缺陷地址数据存储电路输出表示存储单元阵列中的有缺陷的存储单元的地址的第一缺陷地址数据。 第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。 第二缺陷地址数据存储电路输出指示存储单元阵列中缺陷存储单元地址的第二缺陷地址数据。 第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

公开(公告)号：US07782662B2

公开(公告)日：2010-08-24

申请号：US12181926

申请日：2008-07-29

申请人： Masaharu Wada ,  Takehiko Hojo

发明人： Masaharu Wada ,  Takehiko Hojo

IPC分类号： G11C11/50 ,  G11C5/06 ,  G11C11/00

CPC分类号： G11C17/16 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069

摘要： A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through the first contact, the wiring, and the second contact, and changing resistance values of the first contact to write information; and a read switching circuit controlling current for reading information that flows through the first contact, the wiring, and the third contact.

摘要翻译： 存储装置包括：包括具有第一导电性的第一导体的布线; 以及第一，第二和第三触点，每个包括具有第二导电性的第二导体并接触布线。 存储装置还包括：写入切换电路，控制用于写入流经第一触点，布线和第二触点的信息的电流，以及改变第一触点的电阻值以写入信息; 以及读取切换电路，控制用于读取流过第一触点，布线和第三触点的信息的电流。