公开(公告)号：US06614713B2

公开(公告)日：2003-09-02

申请号：US09922670

申请日：2001-08-07

申请人： Tetsushi Tanizaki ,  Katsumi Dosaka ,  Mikio Asakura

发明人： Tetsushi Tanizaki ,  Katsumi Dosaka ,  Mikio Asakura

IPC分类号： G11C800

CPC分类号： G11C29/48 ,  G11C11/406

摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.

摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。

公开(公告)号：US06335645B1

公开(公告)日：2002-01-01

申请号：US09593079

申请日：2000-06-13

申请人： Yukikazu Matsuo ,  Masami Nakajima ,  Tetsushi Tanizaki

发明人： Yukikazu Matsuo ,  Masami Nakajima ,  Tetsushi Tanizaki

IPC分类号： H03L700

CPC分类号： G01R31/3016 ,  H03L7/00

摘要： When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes. Therefore, because the for-synchronization-circuit enabling signal is not received from the outsides but is produced, a circuit area of a semiconductor integrated circuit can be efficiently used.

摘要翻译： 当异步内部时钟使能信号与外部时钟信号异步的电平在外部时钟信号的电平变化之后或之前上升时，与外部时钟信号同步的同步电路使能信号在 条件是在外部时钟信号的两个时钟的外部时钟信号的电平变化晚的同时电路使能信号的电平上升的条件下，控制信号产生电路。 因此，获得从外部时钟信号的电平变化到同步电路使能信号的电平变化的复位时间段。 根据外部时钟信号和异步内部时钟使能信号，在复位时间段中复位同步电路，并且在复位时间允许信号之后，从同步电路使能信号在同步电路中产生测试信号， 期间通行证。 因此，由于没有从外部接收到同步电路使能信号，而是被产生，因此可以有效地使用半导体集成电路的电路区域。

公开(公告)号：US06288956B1

公开(公告)日：2001-09-11

申请号：US09477717

申请日：2000-01-05

申请人： Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

发明人： Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

IPC分类号： G11C1140

CPC分类号： G11C29/46

摘要： A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

摘要翻译： 根据本发明的半导体器件包括多个测试模式电路。 每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。 每个解码电路产生测试模式信号。 测试模式信号保持在锁存电路中。 每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。 因此，多个测试模式信号可以任意和连续地组合。

公开(公告)号：US06215720B1

公开(公告)日：2001-04-10

申请号：US09478528

申请日：2000-01-06

申请人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

发明人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C5/025 ,  G11C7/22 ,  G11C8/12

摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

摘要翻译： 主控制电路通过四个本地控制电路提供对对应存储器块的访问。 存储块被布置成围绕主控制电路和本地控制电路。 控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。 可以实现高速DRAM。

公开(公告)号：US6072743A

公开(公告)日：2000-06-06

申请号：US110688

申请日：1998-07-07

申请人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

发明人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

IPC分类号： G11C5/02 ,  G11C7/22 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C7/222 ,  G11C5/025 ,  G11C7/22 ,  G11C8/12

摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

摘要翻译： 主控制电路通过四个本地控制电路提供对对应存储器块的访问。 存储块被布置成围绕主控制电路和本地控制电路。 将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。 可以实现高速DRAM。

公开(公告)号：US6064621A

公开(公告)日：2000-05-16

申请号：US113147

申请日：1998-07-10

申请人： Tetsushi Tanizaki ,  Mitsuya Kinoshita ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Mako Kobayashi

发明人： Tetsushi Tanizaki ,  Mitsuya Kinoshita ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Mako Kobayashi

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/14 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C8/12

摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.

摘要翻译： 矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。 多个存储器阵列块被分成多个存储体。 矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。 因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

公开(公告)号：US5386387A

公开(公告)日：1995-01-31

申请号：US111818

申请日：1993-08-25

申请人： Tetsushi Tanizaki

发明人： Tetsushi Tanizaki

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/24

摘要： In a semiconductor memory device according to the present invention, the relation between column selection lines and bit line pairs in each memory cell block is defined such that each normal memory cell block and an additional memory cell block share the same column decoder address. Therefore, in a semiconductor memory device having an irregular memory cell array arrangement, it is possible to replace a defective column in any of memory cell blocks by only one type of redundant column.

摘要翻译： 在根据本发明的半导体存储器件中，定义每个存储单元块中的列选择线和位线对之间的关​​系，使得每个正常存储器单元块和附加存储单元块共享相同的列解码器地址。 因此，在具有不规则的存储单元阵列布置的半导体存储器件中，可以通过仅一种类型的冗余列来替换任何存储单元块中的缺陷列。

公开(公告)号：US5297102A

公开(公告)日：1994-03-22

申请号：US950365

申请日：1992-09-24

申请人： Tetsushi Tanizaki

发明人： Tetsushi Tanizaki

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4096

摘要： A DRAM includes a plurality of first memory arrays and a second memory array. The plurality of first memory arrays are arranged in two lines. The second memory array is provided on one end side of a region including memory arrays. Each of first memory arrays is divided into four blocks, and performs 1/4 divisional operation. The second memory array is divided into four blocks and performs 1/2 divisional operation. Refresh operation of the DRAM can be switched to 1024 refresh cycle and 512 refresh cycle. Each of the first memory arrays includes 1024 word lines, and the second memory array includes 512 word lines corresponding to the 512 refresh cycle.

摘要翻译： DRAM包括多个第一存储器阵列和第二存储器阵列。 多个第一存储器阵列被布置成两行。 第二存储器阵列设置在包括存储器阵列的区域的一端侧。 每个第一存储器阵列被分成四个块，并且执行1/4分区操作。 第二存储器阵列被分成四个块并执行1/2分割操作。 DRAM的刷新操作可以切换到1024个刷新周期和512个刷新周期。 每个第一存储器阵列包括1024个字线，并且第二存储器阵列包括对应于512个刷新周期的512个字线。