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113 条记录 (耗时 0.031 秒)

    Semiconductor integrated circuit device having stable input protection circuit
    7.
    发明授权
    Semiconductor integrated circuit device having stable input protection circuit 失效
    半导体集成电路器件具有稳定的输入保护电路

    公开(公告)号：US5909046A

    公开(公告)日：1999-06-01

    申请号：US965618

    申请日：1997-11-06

    申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

    摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

    摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07910975B2

    公开(公告)日：2011-03-22

    申请号：US10593275

    申请日：2005-06-03

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08188534B2

    公开(公告)日：2012-05-29

    申请号：US13022864

    申请日：2011-02-08

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07652927B2

    公开(公告)日：2010-01-26

    申请号：US11797804

    申请日：2007-05-08

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： G11C16/06

    CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

    摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).

    摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。