公开(公告)号：US20130058163A1

公开(公告)日：2013-03-07

申请号：US13418651

申请日：2012-03-13

申请人： Masaru KITO ,  Tomoko FUJIWARA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Tomoko FUJIWARA ,  Hideaki AOCHI

IPC分类号： G11C11/34 ,  H01L29/78

CPC分类号： H01L27/11565 ,  G11C5/025 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。 层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。 半导体柱穿透层叠体。 电荷存储层设置在电极膜和半导体柱之间。 隧道层设置在电荷存储层和半导体柱之间。 在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。 第一加热单元设置在分隔沟槽的内部。

公开(公告)号：US20130020627A1

公开(公告)日：2013-01-24

申请号：US13409652

申请日：2012-03-01

申请人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

公开(公告)号：US20110188307A1

公开(公告)日：2011-08-04

申请号：US13017699

申请日：2011-01-31

申请人： Masaru KITO ,  Hideaki AOCHI

发明人： Masaru KITO ,  Hideaki AOCHI

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/14

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。 存储单元包括电荷存储膜和存储单元晶体管。 针对被配置为在电影中存储电荷的每个存储区域提供晶体管。 控制单元通过设置区域中的擦除信息将晶体管设置为擦除阈值; 随后通过将具有n个值的信息编程到设置有擦除信息的区域中的至少一个来将晶体管设置为对应于具有n个值的信息的阈值; 并且在与所述信息编程的区域相邻编程之前控制至少一个存储区域的信息，以使得具有提供比所述擦除阈值更接近的晶体管的阈值的值到与所述阈值的n值的信息相对应的阈值 设置在该区域中的晶体管被​​设置为对应于具有n值的信息的阈值。

公开(公告)号：US20130234233A1

公开(公告)日：2013-09-12

申请号：US13603797

申请日：2012-09-05

申请人： Tomoko FUJIWARA ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

发明人： Tomoko FUJIWARA ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device comprises a first layer, a first conductive layer, a insulating layer, and a second conductive layer stacked on a substrate, a block insulating layer on inner surfaces of a pair of through-holes formed in the first conductive layer, the insulating layer, and the second conductive layer, and on an inner surface of a connecting hole connecting lower ends of the pair of through-holes, a charge storage layer on the block insulating layer, a second layer on the charge storage layer, and a semiconductor layer on the second layer. The second layer includes an air gap layer on the charge storage layer in the pair of through-holes, and a third conductive layer on the charge storage layer in the connecting hole.

摘要翻译： 根据一个实施例，半导体存储器件包括第一层，第一导电层，绝缘层和堆叠在衬底上的第二导电层，在形成在衬底中的一对通孔的内表面上的块绝缘层 第一导电层，绝缘层和第二导电层，以及连接在一对通孔的下端的连接孔的内表面上，在块绝缘层上的电荷存储层，电荷上的第二层 存储层和第二层上的半导体层。 第二层包括一对通孔中的电荷存储层上的气隙层和连接孔中的电荷存储层上的第三导电层。

公开(公告)号：US20130075918A1

公开(公告)日：2013-03-28

申请号：US13405692

申请日：2012-02-27

申请人： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Tomoko FUJIWARA

发明人： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Tomoko FUJIWARA

IPC分类号： H01L23/48

CPC分类号： B82Y10/00 ,  G11C19/00 ,  G11C19/282 ,  G11C19/38 ,  H01L27/1052 ,  H01L27/1057 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/788

摘要： In one embodiment, a shift register memory includes a substrate, and a channel layer provided on the substrate, and having a helical shape rotating around an axis which is perpendicular to a surface of the substrate. The memory further includes at least three control electrodes provided on the substrate, extending in a direction parallel to the axis, and to be used to transfer charges in the channel layer.

摘要翻译： 在一个实施例中，移位寄存器存储器包括衬底和设置在衬底上的沟道层，并且具有围绕垂直于衬底表面的轴线旋转的螺旋形状。 存储器还包括设置在基板上的至少三个控制电极，其在平行于该轴线的方向上延伸，并用于在沟道层中传送电荷。