公开(公告)号：US20100052042A1

公开(公告)日：2010-03-04

申请号：US12561451

申请日：2009-09-17

申请人： Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDO ,  Masaru KITO ,  Mitsuru SATO

发明人： Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDO ,  Masaru KITO ,  Mitsuru SATO

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。

公开(公告)号：US20130109157A1

公开(公告)日：2013-05-02

申请号：US13723601

申请日：2012-12-21

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US20130058163A1

公开(公告)日：2013-03-07

申请号：US13418651

申请日：2012-03-13

申请人： Masaru KITO ,  Tomoko FUJIWARA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Tomoko FUJIWARA ,  Hideaki AOCHI

IPC分类号： G11C11/34 ,  H01L29/78

CPC分类号： H01L27/11565 ,  G11C5/025 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。 层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。 半导体柱穿透层叠体。 电荷存储层设置在电极膜和半导体柱之间。 隧道层设置在电荷存储层和半导体柱之间。 在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。 第一加热单元设置在分隔沟槽的内部。

公开(公告)号：US20130020627A1

公开(公告)日：2013-01-24

申请号：US13409652

申请日：2012-03-01

申请人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

公开(公告)号：US20120218821A1

公开(公告)日：2012-08-30

申请号：US13463889

申请日：2012-05-04

申请人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

发明人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20120135593A1

公开(公告)日：2012-05-31

申请号：US13366509

申请日：2012-02-06

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20100072538A1

公开(公告)日：2010-03-25

申请号：US12534576

申请日：2009-08-03

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20120064683A1

公开(公告)日：2012-03-15

申请号：US13301442

申请日：2011-11-21

申请人： Megumi ISHIDUKI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

发明人： Megumi ISHIDUKI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US20110188307A1

公开(公告)日：2011-08-04

申请号：US13017699

申请日：2011-01-31

申请人： Masaru KITO ,  Hideaki AOCHI

发明人： Masaru KITO ,  Hideaki AOCHI

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/14

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。 存储单元包括电荷存储膜和存储单元晶体管。 针对被配置为在电影中存储电荷的每个存储区域提供晶体管。 控制单元通过设置区域中的擦除信息将晶体管设置为擦除阈值; 随后通过将具有n个值的信息编程到设置有擦除信息的区域中的至少一个来将晶体管设置为对应于具有n个值的信息的阈值; 并且在与所述信息编程的区域相邻编程之前控制至少一个存储区域的信息，以使得具有提供比所述擦除阈值更接近的晶体管的阈值的值到与所述阈值的n值的信息相对应的阈值 设置在该区域中的晶体管被​​设置为对应于具有n值的信息的阈值。

公开(公告)号：US20100207194A1

公开(公告)日：2010-08-19

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

发明人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。