公开(公告)号：US06861349B1

公开(公告)日：2005-03-01

申请号：US10145944

申请日：2002-05-15

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76874

摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元素进入阻挡材料层上的界面层，在界面层上沉积合金层。 植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

公开(公告)号：US06835655B1

公开(公告)日：2004-12-28

申请号：US09994397

申请日：2001-11-26

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

IPC分类号： H01L2144

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76859 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.

摘要翻译： 在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障 将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。 注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。

公开(公告)号：US06703308B1

公开(公告)日：2004-03-09

申请号：US09994400

申请日：2001-11-26

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76859 ,  H01L21/76867

摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。 植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。 植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

公开(公告)号：US06440868B1

公开(公告)日：2002-08-27

申请号：US09691259

申请日：2000-10-19

申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

IPC分类号： H01L21302

CPC分类号： H01L21/28052 ,  H01L29/517 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后将金属沉积在CVD非晶硅层上。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

公开(公告)号：US06376343B1

公开(公告)日：2002-04-23

申请号：US09812695

申请日：2001-03-21

申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

IPC分类号： H01L21425

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/665

摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

摘要翻译： 避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低 通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类 金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。

公开(公告)号：US06867428B1

公开(公告)日：2005-03-15

申请号：US10282712

申请日：2002-10-29

申请人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

发明人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/6659 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.

摘要翻译： n型应变硅MOSFET利用形成在硅锗衬底上的应变硅沟道区。 在应变硅沟道区的相对侧的硅天竺塔层中设置有硅区，并且在硅区域中注入浅的源极和漏极延伸。 通过在硅区域而不是在硅锗中形成浅的源极和漏极延伸部分，避免了由锗在锗中增加的扩散速率引起的源极和漏极扩展失真。

公开(公告)号：US06432805B1

公开(公告)日：2002-08-13

申请号：US09783620

申请日：2001-02-15

申请人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

发明人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

摘要翻译： 通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理 桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

公开(公告)号：US06815340B1

公开(公告)日：2004-11-09

申请号：US10145928

申请日：2002-05-15

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76874

摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.

摘要翻译： 制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物， 以及使用合金在导电层的暴露部分上形成成核层。 成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

公开(公告)号：US06589866B1

公开(公告)日：2003-07-08

申请号：US09691226

申请日：2000-10-19

申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

IPC分类号： H01L2144

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

公开(公告)号：US06436840B1

公开(公告)日：2002-08-20

申请号：US09691188

申请日：2000-10-19

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。