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21.发明授权Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise 有权二进制加权的delta-sigma分数N频率合成器，具有数字到模拟微分器来消除量化噪声公开(公告)号：US08193845B2
公开(公告)日：2012-06-05
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译： 锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。 量化电路包括数模转换微分器。 数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权 数字到模拟微分器。
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22.发明申请MILLI-METER-WAVE-WIRELESS-INTERCONNECT (M2W2 - INTERCONNECT) METHOD FOR SHORT-RANGE COMMUNICATIONS WITH ULTRA-HIGH DATA CAPABILITY 有权具有超高数据能力的短距离通信的毫米波无线互联（M2W2 - 互连）方法公开(公告)号：US20120082194A1
公开(公告)日：2012-04-05
申请号：US13377124
申请日：2010-06-09
IPC分类号： H04L5/16
CPC分类号： H04B5/0031 , H01L2224/49171 , H04B5/02
摘要： A millimeter wave wireless (M2W2) interconnect is used for transmitting and receiving signals at millimeter-wave frequencies for short-range wireless communication with high data rate capability. The transmitter and receiver antennae may comprise an on-chip differential dipole antenna or a bond wire differential dipole antenna. The bond wire differential dipole antenna is comprised of a pair of bond wires connecting between a pair of pads on an integrated circuit (IC) die and a pair of floating pads on a printed circuit board (PCB).
摘要翻译： 毫米波无线（M2W2）互连用于以毫米波频率发送和接收具有高数据速率能力的短距离无线通信的信号。 发射机和接收机天线可以包括片上差分偶极天线或接合线差分偶极天线。 接合线差分偶极天线由连接在集成电路（IC）管芯上的一对焊盘和印刷电路板（PCB）上的一对浮动焊盘之间的一对接合线组成。
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公开(公告)号：US07965152B2
公开(公告)日：2011-06-21
申请号：US12326791
申请日：2008-12-02
IPC分类号： H01P1/22
CPC分类号： H03H11/24
摘要： An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.
摘要翻译： 衰减器系统包括衰减器和用于控制衰减器的衰减的控制电路。 在一个实施例中，衰减器包括两个二极管或两个二极管连接的晶体管，并且控制电路包括两个晶体管作为唯一有源器件。 在另一实施例中，控制电路包括关闭电路中的另一晶体管。
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24.发明授权Integrated power detector with temperature compensation for fully-closed loop control 有权具有温度补偿功能的集成功率检测器，实现全闭环控制公开(公告)号：US07852063B2
公开(公告)日：2010-12-14
申请号：US12133297
申请日：2008-06-04
IPC分类号： G01R5/22
CPC分类号： G01R21/12 , H03G3/3042 , H03G2201/708
摘要： An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
摘要翻译： 放大器电路包括用于接收RF信号的检测功率输入电路和包括用于响应于参考控制电压产生偏置信号的输出的偏置电路。 功率检测器还包括用于产生具有抵消接收的RF信号的温度特性的电压特性的功率控制电压的检测电路。 放大器电路还包括耦合到偏置电路的功率放大器。 功率放大器包括提供RF信号的驱动级。 检测电路补偿接收到的RF信号的输入检测电压的温度变化。
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25.发明申请SYSTEMS AND METHODS FOR TRANSMISSION AND RECEPTION OF DATA INCLUDING PROCESSING AND BUFFERING FEATURES 审中-公开用于传输和接收数据的系统和方法，包括处理和缓冲特性公开(公告)号：US20080298242A1
公开(公告)日：2008-12-04
申请号：US12060825
申请日：2008-04-01
IPC分类号： H04L7/00
CPC分类号： H04J3/0632 , G10L19/167 , H04J3/12 , H04L1/1835 , H04L1/1867 , H04L47/10 , H04L47/14 , H04L47/22 , H04L47/30
摘要： The present invention relates to a wireless data system which has a transmitter including a transmission buffer. The transmitter is configured to transmit a plurality of packets of encoded data, wherein a level of the transmission buffer is encoded in one of the packets of encoded data. The system further has a wireless receiver for receiving the plurality of packets. The receiver has at least one receiving component that receives the plurality of packets to generate a plurality of decoded signals, wherein the at least one receiving component is configured to receive one of the packets of encoded data from the transmitter to determine the level of transmission buffer. The receiving component is further configured to store the plurality of packets received in a receive buffer, to determine the level of the receive buffer, and to calculate an aggregate buffer level from the transmission buffer and the receive buffer. The receiver controls a packet output rate from the receive buffer to maintain the aggregate buffer level at a desired level.
摘要翻译： 本发明涉及一种具有发送器的无线数据系统，发送器包括发送缓冲器。 发送器被配置为发送多个编码数据分组，其中传输缓冲器的级别被编码在编码数据的分组之一中。 该系统还具有用于接收多个分组的无线接收机。 所述接收机具有接收所述多个分组以生成多个解码信号的至少一个接收组件，其中所述至少一个接收组件被配置为从所述发射机接收编码数据分组中的一个以确定所述发射缓冲器的电平 。 接收组件还被配置为存储在接收缓冲器中接收的多个分组，以确定接收缓冲器的电平，并且从发送缓冲器和接收缓冲器计算聚合缓冲器电平。 接收器控制来自接收缓冲器的分组输出速率，以将聚合缓冲器级别保持在期望的水平。
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26.发明授权Systems and methods for transmission and reception of data including frequency and channel code selection 有权用于发送和接收数据的系统和方法，包括频率和信道码选择公开(公告)号：US07970016B2
公开(公告)日：2011-06-28
申请号：US12060807
申请日：2008-04-01
IPC分类号： H04J1/00
CPC分类号： H04L1/1854 , H04L1/1692
摘要： Systems and methods are disclosed for wireless transmission and reception of data including processing and buffering features. According to one or more exemplary aspects, there is provided a wireless audio receiver for receiving a plurality of packets of encoded audio data. Moreover, the receiver includes at least one receiving component that receives the plurality of packets to generate a plurality of decoded signals, a decoding component that decodes the first packet of encoded data transmitted to produce decoded data, and a selecting component that identifies the mechanisms for receiving additional encoded data. Other exemplary embodiments may include one or more receiving components that processing data regarding antenna, frequencies and channels selected for transmission, as well as an audio component that receives the decoded signals and produces decoded audio signals.
摘要翻译： 公开了用于无线传输和接收包括处理和缓冲特征的数据的系统和方法。 根据一个或多个示例性方面，提供了一种用于接收多个编码音频数据分组的无线音频接收器。 此外，接收机包括接收多个分组以生成多个解码信号的至少一个接收组件，解码发送的第一编码数据分组以产生解码数据的解码部件，以及识别用于 接收附加的编码数据。 其它示例性实施例可以包括处理关于选择用于传输的天线，频率和信道的数据的一个或多个接收组件，以及接收解码信号并产生解码音频信号的音频组件。
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27.发明授权Integrated power detector with temperature compensation for fully-closed loop control 有权具有温度补偿功能的集成功率检测器，实现全闭环控制公开(公告)号：US07893684B2
公开(公告)日：2011-02-22
申请号：US12848937
申请日：2010-08-02
IPC分类号： G01R5/22
CPC分类号： G01R21/12 , H03G3/3042 , H03G2201/708
摘要： An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
摘要翻译： 放大器电路包括用于接收RF信号的检测功率输入电路和包括用于响应于参考控制电压产生偏置信号的输出的偏置电路。 功率检测器还包括用于产生具有抵消接收的RF信号的温度特性的电压特性的功率控制电压的检测电路。 放大器电路还包括耦合到偏置电路的功率放大器。 功率放大器包括提供RF信号的驱动级。 检测电路补偿接收到的RF信号的输入检测电压的温度变化。
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公开(公告)号：US20100271136A1
公开(公告)日：2010-10-28
申请号：US12428362
申请日：2009-04-22
IPC分类号： H03F3/14
CPC分类号： H03F3/195 , H03F1/302 , H03F2200/18
摘要： A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process. The second functional block may be a power amplifier formed by a heterojunction bipolar transistor process. In another aspect, the first functional block may be a power amplifier formed by a heterojunction bipolar transistor process. The second functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.
摘要翻译： 前端模块包括多个芯片，其包括第一和第二功能块以及互连电路。 第一功能块使用第一处理类型形成，并且包括响应于来自前端模块外部的外部控制信号而生成数字控制信号的数字控制电路。 第二功能块使用第二处理类型形成，并且包括由第一功能块生成的数字控制信号控制的数字控制电路。 第二种处理类型与第一种类型不同。 互连电路耦合数字控制电路和数字控制电路，以向数字控制电路提供数字控制信号。 在一个方面，第一功能块可以是由伪像高电子迁移率晶体管工艺形成的低噪声放大器。 第二功能块可以是由异质结双极晶体管工艺形成的功率放大器。 在另一方面，第一功能块可以是由异质结双极晶体管工艺形成的功率放大器。 第二功能块可以是由伪像高电子迁移率晶体管工艺形成的低噪声放大器。
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公开(公告)号：US20080122074A1
公开(公告)日：2008-05-29
申请号：US11605890
申请日：2006-11-28
CPC分类号： H01L25/16 , H01L24/19 , H01L2224/04105 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/09701 , H01L2924/1301 , H01L2924/14 , H01L2924/15787 , H01L2924/19015 , H01L2924/19105 , H01L2924/00
摘要： An integrated circuit module has a substrate with an exposed surface. An integrated circuit die has a first surface and a second surface opposite the first surface, and has a plurality of bonding pads on the second surface. The integrated circuit die is positioned with its first surface on the exposed surface of the substrate. A plurality of dielectric layers cover the second surface of the integrated circuit die. At least one conductive layer is sandwiched between a pair of the plurality of dielectric layers, and forms one or more passive elements electrically connected to the plurality of bonding pads of the integrated circuit die, through one or more holes in one of the plurality of dielectric layers.
摘要翻译： 集成电路模块具有具有暴露表面的基板。 集成电路管芯具有与第一表面相对的第一表面和第二表面，并且在第二表面上具有多个接合焊盘。 集成电路管芯的第一表面位于衬底的暴露表面上。 多个电介质层覆盖集成电路管芯的第二表面。 至少一个导电层夹在一对多个电介质层之间，并通过多个电介质层之一中的一个或多个孔形成电连接到集成电路管芯的多个接合焊盘的一个或多个无源元件 层。
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30.发明申请Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise 有权二进制加权Delta-Sigma分数N频率合成器，具有数字到模拟差分器取消量化噪声公开(公告)号：US20120007643A1
公开(公告)日：2012-01-12
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/08
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译： 锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。 量化电路包括数模转换微分器。 数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权 数字到模拟微分器。
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