公开(公告)号：US11764096B2

公开(公告)日：2023-09-19

申请号：US16923754

申请日：2020-07-08

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/4814 ,  H01L23/481

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US20210183806A1

公开(公告)日：2021-06-17

申请号：US16715594

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29

Abstract: Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies.

公开(公告)号：US20210183702A1

公开(公告)日：2021-06-17

申请号：US16713309

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/50

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

公开(公告)号：US20210167030A1

公开(公告)日：2021-06-03

申请号：US17174905

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  David R. Hembree

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

公开(公告)号：US10923447B2

公开(公告)日：2021-02-16

申请号：US15603175

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  David R. Hembree

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

公开(公告)号：US10825762B2

公开(公告)日：2020-11-03

申请号：US16200873

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

公开(公告)号：US10276479B1

公开(公告)日：2019-04-30

申请号：US15730272

申请日：2017-10-11

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/12 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768

Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

公开(公告)号：US20250046730A1

公开(公告)日：2025-02-06

申请号：US18781737

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Owen R. Fay ,  Cassie L. Bayless

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/3115 ,  H01L21/32 ,  H01L23/00

Abstract: Methods, apparatuses, and systems related to a semiconductor structure having an implanted alignment mark. The alignment mark may be formed by implanting a distinguishable material within a thickness of an initial semiconductor wafer and then thinning the initial semiconductor wafer. The distinguishable material may be implanted during, as a part of, or shortly following frontside processing to form active circuitry or portions thereof and then subsequently exposed through the thinning process. The resulting mark may be used to identify a relative location of circuits on the thinned wafer for subsequent processing or bonding.

公开(公告)号：US11961818B2

公开(公告)日：2024-04-16

申请号：US17817803

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16221 ,  H01L2224/16238 ,  H01L2224/75263 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2225/06517

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

公开(公告)号：US11715696B2

公开(公告)日：2023-08-01

申请号：US17237496

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L25/0657

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.