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    Package-on-package semiconductor assemblies and methods of manufacturing the same
    2.
    发明授权
    Package-on-package semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US11139229B2

    公开(公告)日：2021-10-05

    申请号：US16536490

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    Electronic devices having tapered edge walls
    3.
    发明授权
    Electronic devices having tapered edge walls 有权

    公开(公告)号：US10825761B2

    公开(公告)日：2020-11-03

    申请号：US16200843

    申请日：2018-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Jack E. Murray

    IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

    Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.

    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220028771A1

    公开(公告)日：2022-01-27

    申请号：US17493352

    申请日：2021-10-04

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    Methods of processing semiconductor devices
    5.
    发明授权
    Methods of processing semiconductor devices 有权

    公开(公告)号：US10825762B2

    公开(公告)日：2020-11-03

    申请号：US16200873

    申请日：2018-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Jack E. Murray

    IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

    Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

    Methods of processing semiconductor devices
    6.
    发明授权
    Methods of processing semiconductor devices 有权

    公开(公告)号：US10276479B1

    公开(公告)日：2019-04-30

    申请号：US15730272

    申请日：2017-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Jack E. Murray

    IPC: H01L23/12 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768

    Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

    METHODS OF PROCESSING SEMICONDUCTOR DEVICES
    7.
    发明申请
    METHODS OF PROCESSING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190109081A1

    公开(公告)日：2019-04-11

    申请号：US16200873

    申请日：2018-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/768 ,  H01L21/48

    Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

    METHODS OF PROCESSING SEMICONDUCTOR DEVICES
    8.
    发明申请
    METHODS OF PROCESSING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190109079A1

    公开(公告)日：2019-04-11

    申请号：US15730272

    申请日：2017-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768

    Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

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