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公开(公告)号:US20220262820A1
公开(公告)日:2022-08-18
申请号:US17661659
申请日:2022-05-02
Applicant: Micron Technology, Inc.
Inventor: Matthew J. King , David A. Daycock , Yoshiaki Fukuzumi , Albert Fayrushin , Richard J. Hill , Chandra S. Tiwari , Jun Fujiki
IPC: H01L27/11582 , H01L29/06 , H01L21/762
Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.
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22.
公开(公告)号:US11276658B2
公开(公告)日:2022-03-15
申请号:US16987223
申请日:2020-08-06
Applicant: Micron Technology, Inc.
Inventor: Christopher J. Gambee , Nhi Doan , Chandra S. Tiwari , Owen R. Fay , Ying Chen
IPC: H01L23/00 , H01L21/027 , H01L21/56
Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.
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公开(公告)号:US11094684B2
公开(公告)日:2021-08-17
申请号:US16514159
申请日:2019-07-17
Applicant: Micron Technology, Inc.
Inventor: Chandra S. Tiwari , Tony M. Lindenberg , Jonathan S. Hacker , Christopher J. Gambee , Kurt J. Bossart
IPC: H01L25/00 , H01L23/00 , H01L21/02 , H01L21/683
Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.
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24.
公开(公告)号:US10852344B2
公开(公告)日:2020-12-01
申请号:US15839559
申请日:2017-12-12
Applicant: Micron Technology, Inc.
Inventor: Tony M. Lindenberg , Kurt J. Bossart , Jonathan S. Hacker , Chandra S. Tiwari
Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.
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25.
公开(公告)号:US20190393176A1
公开(公告)日:2019-12-26
申请号:US16013237
申请日:2018-06-20
Applicant: Micron Technology, Inc.
Inventor: Christopher J. Gambee , Nhi Doan , Chandra S. Tiwari , Owen R. Fay , Ying Chen
IPC: H01L23/00 , H01L21/027 , H01L21/56
Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.
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26.
公开(公告)号:US20190178933A1
公开(公告)日:2019-06-13
申请号:US15839559
申请日:2017-12-12
Applicant: Micron Technology, Inc.
Inventor: Tony M. Lindenberg , Kurt J. Bossart , Jonathan S. Hacker , Chandra S. Tiwari
Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.
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27.
公开(公告)号:US20190051623A1
公开(公告)日:2019-02-14
申请号:US15982129
申请日:2018-05-17
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L25/065 , H01L21/66
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
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