公开(公告)号：US20200075630A1

公开(公告)日：2020-03-05

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US10438962B2

公开(公告)日：2019-10-08

申请号：US15933218

申请日：2018-03-22

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/11 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L27/11582 ,  H01L29/51

Abstract: Some embodiments include an assembly having a channel to conduct current. The channel includes a first channel portion and a second channel portion. A first memory cell structure is between a first gate and the first channel portion. The first memory cell structure includes a first charge-storage region and a first charge-blocking region. A second memory cell structure is between a second gate and the second channel portion. The second memory cell structure includes a second charge-storage region and a second charge-blocking region. The first and second charge-blocking regions include silicon oxynitride. A void is located between the first and second gates, and between the first and second memory cell structures. Some embodiments include memory arrays (e.g., NAND memory arrays), and some embodiments include methods of forming memory arrays.

公开(公告)号：US20190198510A1

公开(公告)日：2019-06-27

申请号：US15933218

申请日：2018-03-22

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/762

Abstract: Some embodiments include an assembly having a channel to conduct current. The channel includes a first channel portion and a second channel portion. A first memory cell structure is between a first gate and the first channel portion. The first memory cell structure includes a first charge-storage region and a first charge-blocking region. A second memory cell structure is between a second gate and the second channel portion. The second memory cell structure includes a second charge-storage region and a second charge-blocking region. The first and second charge-blocking regions include silicon oxynitride. A void is located between the first and second gates, and between the first and second memory cell structures. Some embodiments include memory arrays (e.g., NAND memory arrays), and some embodiments include methods of forming memory arrays.

公开(公告)号：US20190198509A1

公开(公告)日：2019-06-27

申请号：US15855089

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).