公开(公告)号：US11871575B2

公开(公告)日：2024-01-09

申请号：US17806829

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. McKinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US11785775B2

公开(公告)日：2023-10-10

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/562 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US11665894B2

公开(公告)日：2023-05-30

申请号：US17249552

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  Lifang Xu

IPC: H10B41/27 ,  H10B43/27 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06

CPC classification number: H01L27/11556 ,  G11C5/06 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/11582

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220285378A1

公开(公告)日：2022-09-08

申请号：US17249552

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  Lifang XU

IPC: H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20130260521A1

公开(公告)日：2013-10-03

申请号：US13902052

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Christopher J. Larsen

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66833

Abstract: A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor.

Abstract translation: 形成存储器阵列的方法包括在半导体上形成电介质，在电介质上形成电荷存储结构，通过电介质和电荷存储结构形成隔离区并延伸到半导体中，使隔离区凹陷到 电平低于电介质的上表面的电平并且在半导体的上表面的水平以上，在电荷存储结构和凹陷隔离区域上形成存取线，并且在凹陷隔离件上形成气隙 区域，使得气隙通过电荷存储结构，使得气隙延伸到并终止于进入管线的底表面，并且使得整个气隙位于进入管线的底表面和 半导体的上表面。