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公开(公告)号：US20240185938A1
公开(公告)日：2024-06-06
申请号：US18516121
申请日：2023-11-21
Applicant: Micron Technology, Inc.
Inventor： Niccolò Izzo , David Hulton , Tamara Schmitz , Angelo Alberto Rovelli , Craig A. Jones , Danilo Caraccio
CPC classification number: G11C29/08 , G11C29/023
Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
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公开(公告)号：US20230394143A1
公开(公告)日：2023-12-07
申请号：US18104079
申请日：2023-01-31
Applicant: Micron Technology, Inc
Inventor： Aaron P. Boehm , David Hulton , Jeremy Chritz , Tamara Schmitz , Max S. Vohra
CPC classification number: G06F21/556 , G06F21/575 , G06F21/79
Abstract: Methods, systems, and devices for protective actions for a memory device based on detecting an attack are described. In some systems, a memory device may detect whether a fault is injected into the memory device. The memory device may apply a delay during boot up if a fault is detected. To ensure the delay is applied, the memory device may default to applying the delay and may remove an indication to apply the delay if a fault is not detected. Additionally or alternatively, the memory device may erase information from non-volatile memory during boot up, for example, if a fault is detected. The memory device may be configured to ensure at least a specific portion of memory resources (e.g., resources configured to store sensitive information) is erased during boot up. In some examples, the memory device may store data using a stream cipher to improve security of the data.
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23.发明授权公开(公告)号：US11784923B2
公开(公告)日：2023-10-10
申请号：US17517544
申请日：2021-11-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jeremy Chritz , David Hulton , John Schroeter , John Watson
IPC: H04L45/44 , H04L45/12 , H04L45/00 , H04L45/02 , H04L45/122
CPC classification number: H04L45/44 , H04L45/12 , H04L45/124 , H04L45/04 , H04L45/122 , H04L45/14 , H04L45/22
Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.
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24.发明授权公开(公告)号：US11636285B2
公开(公告)日：2023-04-25
申请号：US17016074
申请日：2020-09-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Hulton , Jeremy Chritz , Tamara Schmitz
Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory die. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing command, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed on a memory die itself, like a memory die of a NAND memory device.
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公开(公告)号：US11609853B2
公开(公告)日：2023-03-21
申请号：US17016053
申请日：2020-09-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Hulton , Jeremy Chritz , Tamara Schmitz
IPC: G06F12/0802 , G06F13/16
Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory controller with various memory devices. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at the memory controller coupled to memory devices.
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Patent Agency Ranking
公开(公告)号：US11586380B2
公开(公告)日：2023-02-21
申请号：US17016023
申请日：2020-09-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Hulton , Jeremy Chritz , Tamara Schmitz
Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.
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公开(公告)号：US11327682B2
公开(公告)日：2022-05-10
申请号：US17016023
申请日：2020-09-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Hulton , Jeremy Chritz
Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.
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公开(公告)号：US20200057638A1
公开(公告)日：2020-02-20
申请号：US16104341
申请日：2018-08-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Hulton
IPC: G06F9/30
Abstract: An apparatus in a configurable logic unit may include a configurable logic unit (CLU) configured to receive first and second operands and to perform an operand operation and generate an operation value. The apparatus may also include: a random value generator for generating a random value; an adder coupled to the CLU and the random value generator and configured to generate a sum of the operation value and the random value; and a shift register coupled to the adder and configured to shift the sum by a number of bits to generate shifted data at an output. The random value generator may be a linear feedback shift register. The output may be coupled to an additional CLU so that the shifted data may be used for subsequent operand operations. The apparatus may be implemented in a digital signal processor slice in a configurable logic block.
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公开(公告)号：US20190108019A1
公开(公告)日：2019-04-11
申请号：US16116869
申请日：2018-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gregory Edvenson , David Hulton , Jeremy Chritz
Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.
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公开(公告)号：US20250013458A1
公开(公告)日：2025-01-09
申请号：US18894289
申请日：2024-09-24
Applicant: Micron Technology, Inc.
Inventor： Niccolo Izzo , Alessandro Orlando , Danilo Caraccio , David Hulton
Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.
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