公开(公告)号：US11721606B2

公开(公告)日：2023-08-08

申请号：US17196667

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Pengyuan Zheng

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/3736 ,  H01L21/0234 ,  H01L21/02186 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

公开(公告)号：US20230121315A1

公开(公告)日：2023-04-20

申请号：US18083428

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B41/27

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20220310524A1

公开(公告)日：2022-09-29

申请号：US17216210

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett Allen McTeer ,  John Hopkins ,  David Ross Economy

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; an additional dielectric material contacting the portion of the pillar; a conductive material contacting the additional dielectric material; and a tungsten structure including a portion of tungsten contacting the conductive material, wherein a majority of the portion of tungsten is beta-phase tungsten.

公开(公告)号：US10916564B2

公开(公告)日：2021-02-09

申请号：US16866236

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/1157

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US20210005732A1

公开(公告)日：2021-01-07

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20200266210A1

公开(公告)日：2020-08-20

申请号：US16866236

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11556

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US10475810B2

公开(公告)日：2019-11-12

申请号：US16023124

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Sudip Bandyopadhyay ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Anurag Jindal ,  David Ross Economy ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

公开(公告)号：US20180308861A1

公开(公告)日：2018-10-25

申请号：US16023124

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Sudip Bandyopadhyay ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Anurag Jindal ,  David Ross Economy ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/528

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

公开(公告)号：US10014319B1

公开(公告)日：2018-07-03

申请号：US15679499

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Sudip Bandyopadhyay ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Anurag Jindal ,  David Ross Economy ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

公开(公告)号：US09773807B1

公开(公告)日：2017-09-26

申请号：US15455859

申请日：2017-03-10

Applicant: Micron Technology, Inc.

Inventor： Sudip Bandyopadhyay ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Anurag Jindal ,  David Ross Economy ,  John Mark Meldrim

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.