公开(公告)号：US20210351197A1

公开(公告)日：2021-11-11

申请号：US17385201

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/04

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US10892268B2

公开(公告)日：2021-01-12

申请号：US16421262

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L21/28 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US10854747B2

公开(公告)日：2020-12-01

申请号：US16412710

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/16 ,  H01L29/20 ,  H01L29/10 ,  H01L21/321 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190371815A1

公开(公告)日：2019-12-05

申请号：US16437781

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/02

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US20190280122A1

公开(公告)日：2019-09-12

申请号：US16412710

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/78 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11524 ,  H01L29/20 ,  H01L29/16 ,  H01L29/10 ,  H01L27/11556

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10381365B2

公开(公告)日：2019-08-13

申请号：US15677914

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L27/115 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US20180108670A1

公开(公告)日：2018-04-19

申请号：US15295577

申请日：2016-10-17

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A method of forming poly silicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first poly silicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20170373081A1

公开(公告)日：2017-12-28

申请号：US15677914

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US20170053986A1

公开(公告)日：2017-02-23

申请号：US14827695

申请日：2015-08-17

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Gavin Huang

IPC: H01L29/10 ,  H01L29/165 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract translation: 一些实施例包括具有交替介电水平和导电水平的叠层并且在导电水平内具有垂直堆叠的存储器单元的集成结构。 一个开口延伸穿过堆叠。 通道材料在开口内并沿着存储单元。 至少一些通道材料含有锗。