-
公开(公告)号：US20140239931A1
公开(公告)日：2014-08-28
申请号：US14269349
申请日：2014-05-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan
IPC: G11C5/14
CPC classification number: G11C5/147 , Y10T307/735 , Y10T307/74 , Y10T307/766 , Y10T307/826
Abstract: Embodiments described include voltage generators having reduced or eliminated cross current. Dynamic adjustment of a low or high threshold voltage used in a voltage generator is described. Use of a folded cascade amplifier in a voltage generator is also described.
Abstract translation: 所描述的实施例包括具有减少或消除的交叉电流的电压发生器。 描述了在电压发生器中使用的低或高阈值电压的动态调整。 还描述了在电压发生器中使用折叠级联放大器。
-
公开(公告)号：US20230410877A1
公开(公告)日：2023-12-21
申请号：US17844207
申请日：2022-06-20
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4074
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.
-
公开(公告)号：US11721387B2
公开(公告)日：2023-08-08
申请号：US17864237
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C7/14 , G11C11/4074 , G11C11/4091 , H03H7/06 , G11C5/14 , G05F1/575 , G11C11/4063
CPC classification number: G11C11/4074 , G05F1/575 , G11C5/147 , G11C7/14 , G11C11/4063 , G11C11/4091 , H03H7/06
Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.
-
公开(公告)号：US20230206989A1
公开(公告)日：2023-06-29
申请号：US17565187
申请日：2021-12-29
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/408 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C11/406
CPC classification number: G11C11/4082 , G11C11/4091 , G11C11/4094 , G11C11/4087 , G11C11/4096 , G11C11/4097 , G11C11/40611
Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.
-
公开(公告)号：US11545940B2
公开(公告)日：2023-01-03
申请号：US17243762
申请日：2021-04-29
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
Abstract: Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.
-
Patent Agency Ranking
公开(公告)号：US20220311335A1
公开(公告)日：2022-09-29
申请号：US17840434
申请日：2022-06-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
-
公开(公告)号：US11374488B2
公开(公告)日：2022-06-28
申请号：US16321769
申请日：2018-12-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
-
公开(公告)号：US11276476B1
公开(公告)日：2022-03-15
申请号：US17117877
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Dong Pan
Abstract: Systems and methods are provided that sense a state of a fuse located in a fuse array. These methods involve a logic gate that selectively transmits outputs from respective comparators based on the combination of outputs received at the logic gate. The comparators generate outputs based on comparing a signal received indicative of the fuse state and a reference voltage. The described systems and methods reduce power consumption of a fuse sensing device since portions of the fuse sensing device are deactivated when not sensing and enable single fuse reading to occur, among other advantages.
-
29.发明申请公开(公告)号：US20210335411A1
公开(公告)日：2021-10-28
申请号：US17324621
申请日：2021-05-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406
Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.
-
公开(公告)号：US20210158860A1
公开(公告)日：2021-05-27
申请号：US17168036
申请日：2021-02-04
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
-
-
-
-
-
-
-
-
-
Search Results
125
records
(took 0.024 seconds)
