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公开(公告)号：US20160111167A1
公开(公告)日：2016-04-21
申请号：US14518727
申请日：2014-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
IPC: G11C16/26
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读取操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。
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公开(公告)号：US10951114B2
公开(公告)日：2021-03-16
申请号：US16019372
申请日：2018-06-26
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Michele Piccardi
Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.
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公开(公告)号：US10305381B2
公开(公告)日：2019-05-28
申请号：US15721985
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
Abstract: A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle of the digital switch regulator.
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公开(公告)号：US20170163147A1
公开(公告)日：2017-06-08
申请号：US15440564
申请日：2017-02-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
IPC: H02M3/07
CPC classification number: H02M3/07 , H02M3/073 , H02M2001/0048 , H02M2003/075 , H02M2003/076 , Y02B70/1491
Abstract: Methods of operating voltage generation circuits include applying a clock signal to a first electrode of a first capacitance having a second electrode connected to a first node of a first current path, applying the clock signal to a second capacitance having a second electrode connected to a gate of a second current path connected in parallel with the first current path and with the second electrode further connected to a first end of a resistance having a second end connected to the second node, passing charge across at least one of the first current path and the second current path while the clock signal has a first logic phase, and mitigating current flow across the first current path and the second current path while the clock signal has a second logic phase opposite the first logic phase, as well as apparatus facilitating such methods.
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公开(公告)号：US20170162269A1
公开(公告)日：2017-06-08
申请号：US15436289
申请日：2017-02-17
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
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Patent Agency Ranking
公开(公告)号：US20170012523A1
公开(公告)日：2017-01-12
申请号：US14796743
申请日：2015-07-10
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Michele Piccardi
IPC: H02M3/07
Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.
Abstract translation: 本发明的某些实施例包括一种包括电荷泵的装置，其被配置为在电荷泵的输出节点处提供输出电压，以及耦合到电荷泵的电荷泵调节器电路。 一个这样的电荷泵调节器电路被配置为控制电荷泵在第一时间段期间增加输出电压。 这种电荷泵调节器电路还可以使得耦合到电荷泵的输出节点的电路的节点在第二时间段期间达到目标电压电平。
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公开(公告)号：US20160181915A1
公开(公告)日：2016-06-23
申请号：US14581710
申请日：2014-12-23
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Ramin Ghodsi
IPC: H02M3/156
Abstract: Some embodiments include apparatuses having a switch regulator that includes a first circuit with a first comparator to compare an output of the switch regulator to a first reference voltage, and to provide a control signal to enable or disable a first pass element based on the comparison. The switch regulator includes at least a second circuit having a second comparator to compare an output of the switch regulator to a second reference voltage that is lower than the first reference voltage, and to provide a control signal to enable or disable a second pass element based on the comparison. The switch regulator does not include Miller compensation circuits. Other apparatuses and methods according to other embodiments are described.
Abstract translation: 一些实施例包括具有开关调节器的装置，该开关调节器包括具有第一比较器的第一电路，用于将开关调节器的输出与第一参考电压进行比较，并且基于该比较来提供控制信号以启用或禁用第一通过元件。 开关调节器至少包括具有第二比较器的第二电路，用于将开关调节器的输出与低于第一参考电压的第二参考电压进行比较，并且提供控制信号以使第二通过元件基于 比较。 开关稳压器不包括米勒补偿电路。 描述根据其他实施例的其他装置和方法。
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公开(公告)号：US09337776B1
公开(公告)日：2016-05-10
申请号：US14581682
申请日：2014-12-23
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Ramin Ghodsi
CPC classification number: H03F1/0205 , G11C5/145 , G11C7/062 , H03F3/45183 , H03F3/45632 , H03F2203/45081 , H03F2203/45482 , H03F2203/45674
Abstract: The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and a method of operating same. An example level-shifting circuit includes a first transistor and a second transistor to receive a first differential amplifier input. The first transistor has a drain receiving a power input, and the second transistor has a drain coupled to a source of the first transistor and a source coupled to a biased tail circuit. The example level-shifting circuit further includes a third transistor and a fourth transistor to receive a second differential amplifier input. The third transistor has a drain receiving a power input and the fourth transistor has a drain coupled to a source of the third transistor and a source coupled to the biased tail circuit. Other examples, methods, and apparatuses are described herein.
Abstract translation: 本发明公开了一种向差分放大电路提供初始级的电平移位电路，差分放大电路及其操作方法。 示例电平移位电路包括用于接收第一差分放大器输入的第一晶体管和第二晶体管。 第一晶体管具有接收功率输入的漏极，并且第二晶体管具有耦合到第一晶体管的源极的漏极和耦合到偏置尾部电路的源极。 示例电平移位电路还包括第三晶体管和第四晶体管，以接收第二差分放大器输入。 第三晶体管具有接收功率输入的漏极，并且第四晶体管具有耦合到第三晶体管的源极的漏极和耦合到偏置尾部电路的源极。 本文描述了其它示例，方法和装置。
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公开(公告)号：US20160099048A1
公开(公告)日：2016-04-07
申请号：US14868604
申请日：2015-09-29
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Feng Pan , Ramin Ghodsi , Mark A. Helm
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C7/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
Abstract translation: 描述了用于阈值电压（Vt）分布测定的装置和方法。 许多设备可以包括感测电路，其被配置为确定存储器单元阵列的源极线上的第一电流，第一电流对应于响应于第一感测而导通的一组存储器单元的第一数量的存储器单元 施加到访问线路的电压并确定源极线路上的第二电流，第二电流对应于响应于施加到接入线路的第二感测电压而导通的组中的第二数量的存储器单元。 设备的数量可以包括控制器，其被配置为至少部分地基于第一电流和第二电流来确定对应于该组存储器单元的Vt分布的至少一部分。
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公开(公告)号：US10381080B2
公开(公告)日：2019-08-13
申请号：US15280301
申请日：2016-09-29
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Jaekwan Park , Ramin Ghodsi
Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
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