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公开(公告)号：US20180323704A1
公开(公告)日：2018-11-08
申请号：US16019372
申请日：2018-06-26
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Michele Piccardi
Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.
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公开(公告)号：US09780654B2
公开(公告)日：2017-10-03
申请号：US14657545
申请日：2015-03-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
CPC classification number: H02M3/158 , G11C5/147 , G11C16/30 , H02M2001/0045
Abstract: A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle of the digital switch regulator.
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公开(公告)号：US09460792B2
公开(公告)日：2016-10-04
申请号：US14518807
申请日：2014-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Jaekwan Park , Ramin Ghodsi
CPC classification number: G11C16/0483 , G11C8/12 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.
Abstract translation: 描述了分段SGS线的装置和方法。 示例性装置可以包括存储器块的第一和第二多个存储器子块。 该装置可以包括与第一多个存储器子块相关联的第一选择栅极控制线和与第二多个存储器子块相关联的第二选择栅极控制线。 第一选择栅极控制线可以耦合到第一多个存储器子块的第一多个选择栅极开关。 第二选择栅极控制线可以耦合到第二多个存储器子块的第二多个选择栅极开关。 第一和第二多个选择栅极开关可以耦合到源极。 该装置可以包括与每个第一和第二多个存储器子块相关联的多个存储器访问线。
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公开(公告)号：US20160268897A1
公开(公告)日：2016-09-15
申请号：US14657545
申请日：2015-03-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
IPC: H02M3/158
CPC classification number: H02M3/158 , G11C5/147 , G11C16/30 , H02M2001/0045
Abstract: A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle of the digital switch regulator.
Abstract translation: 一种设备包括数字开关调节器，用于基于参考电压向负载提供输出电压和第一电流。 该装置还包括一个模拟电路，用于基于数字开关调节器的占空比，除了第一电流之外还向负载提供第二电流。
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公开(公告)号：US11145370B2
公开(公告)日：2021-10-12
申请号：US17065655
申请日：2020-10-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Jaekwan Park , Ramin Ghodsi
Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
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Patent Agency Ranking
公开(公告)号：US10803945B2
公开(公告)日：2020-10-13
申请号：US16457611
申请日：2019-06-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Jaekwan Park , Ramin Ghodsi
Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
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公开(公告)号：US10404161B2
公开(公告)日：2019-09-03
申请号：US15440564
申请日：2017-02-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
Abstract: Methods of operating voltage generation circuits include applying a clock signal to a first electrode of a first capacitance having a second electrode connected to a first node of a first current path, applying the clock signal to a second capacitance having a second electrode connected to a gate of a second current path connected in parallel with the first current path and with the second electrode further connected to a first end of a resistance having a second end connected to the second node, passing charge across at least one of the first current path and the second current path while the clock signal has a first logic phase, and mitigating current flow across the first current path and the second current path while the clock signal has a second logic phase opposite the first logic phase, as well as apparatus facilitating such methods.
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公开(公告)号：US09697912B2
公开(公告)日：2017-07-04
申请号：US15164956
申请日：2016-05-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Shigekazu Yamada
CPC classification number: G11C29/50 , G11C16/06 , G11C29/025 , G11C2029/5006
Abstract: A first switch is closed to initialize a circuit by charging a capacitance of the circuit. A second switch is closed to initialize an amplifier in unity-gain configuration. The amplifier is capacitively coupled to the circuit. The first switch and the second switch are then opened to detect a leakage current of the circuit by detecting a change in an output voltage of the amplifier.
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公开(公告)号：US09621032B2
公开(公告)日：2017-04-11
申请号：US14813883
申请日：2015-07-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan
CPC classification number: H02M3/07 , H02M3/073 , H02M2001/0048 , H02M2003/075 , H02M2003/076 , Y02B70/1491
Abstract: Voltage generation circuits are useful in the generation of internal voltages for use in integrated circuits. Voltage generation circuits may include a stage capacitance and a voltage isolation device connected to the stage capacitance. The voltage isolation device may include a first current path between an input and an output of the voltage isolation device through a diode, and a second current path between the input and the output of the voltage isolation device through a gate. The gate is responsive to the contribution of a low-pass filter between the output of the voltage isolation device and the gate, and to the contribution of a high-pass filter between a clock signal node and the gate.
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公开(公告)号：US09595339B2
公开(公告)日：2017-03-14
申请号：US14518727
申请日：2014-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。
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