-
公开(公告)号：US20220020448A1
公开(公告)日：2022-01-20
申请号：US17387335
申请日：2021-07-28
IPC分类号： G11C29/42 , G11C29/44 , G11C5/02 , G11C11/4074 , G11C11/4091 , G11C29/02
摘要： Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.
-
公开(公告)号：US11074956B1
公开(公告)日：2021-07-27
申请号：US16806942
申请日：2020-03-02
发明人： Huy T. Vo , Ferdinando Bedeschi , Suryanarayana B. Tatapudi , Hyunyoo Lee , Adam S. El-Mansouri
IPC分类号： G11C11/22
摘要： Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.
-
公开(公告)号：US11003365B2
公开(公告)日：2021-05-11
申请号：US16555546
申请日：2019-08-29
摘要： Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
-
公开(公告)号：US20200327926A1
公开(公告)日：2020-10-15
申请号：US16379222
申请日：2019-04-09
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/408 , H01L27/108
摘要： Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
-
公开(公告)号：US10658035B2
公开(公告)日：2020-05-19
申请号：US16279585
申请日：2019-02-19
IPC分类号： G11C13/00
摘要： A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
-
公开(公告)号：US20200098413A1
公开(公告)日：2020-03-26
申请号：US16592630
申请日：2019-10-03
IPC分类号： G11C11/22 , G11C11/4091 , G11C7/06 , G11C5/14 , G11C11/404 , G11C11/409 , G11C11/408 , G11C7/10
摘要： Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.
-
公开(公告)号：US20190391751A1
公开(公告)日：2019-12-26
申请号：US16555546
申请日：2019-08-29
摘要： Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
-
公开(公告)号：US10446232B2
公开(公告)日：2019-10-15
申请号：US15846373
申请日：2017-12-19
摘要： The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
-
公开(公告)号：US20190244652A1
公开(公告)日：2019-08-08
申请号：US16387208
申请日：2019-04-17
发明人： Ferdinando Bedeschi
IPC分类号： G11C11/22 , H01L27/11502 , H01L27/11514
摘要： Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.
-
公开(公告)号：US10332910B2
公开(公告)日：2019-06-25
申请号：US15944270
申请日：2018-04-03
发明人： Ferdinando Bedeschi
IPC分类号： G11C15/02 , H01L27/11597 , H01L29/78 , H01L27/1159 , H01L27/11587 , H01L29/423 , H01L27/1157 , H01L27/11582
摘要： A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
-
-
-
-
-
-
-
-
-
搜索结果
292 条记录 (耗时 0.03 秒)
