公开(公告)号：US12249364B2

公开(公告)日：2025-03-11

申请号：US17890040

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Tomoharu Tanaka ,  Eric N. Lee ,  Dung V. Nguyen ,  David Ebsen

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

公开(公告)号：US20250077416A1

公开(公告)日：2025-03-06

申请号：US18781838

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

IPC: G06F12/02

Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

公开(公告)号：US11960722B2

公开(公告)日：2024-04-16

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20240062799A1

公开(公告)日：2024-02-22

申请号：US17890040

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Tomoharu Tanaka ,  Eric N. Lee ,  Dung V. Nguyen ,  David Ebsen

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/4085

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

公开(公告)号：US20240028200A1

公开(公告)日：2024-01-25

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20230360705A1

公开(公告)日：2023-11-09

申请号：US18138551

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Akira Goda

IPC: G11C16/12 ,  G11C16/08

CPC classification number: G11C16/12 ,  G11C16/08

Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

公开(公告)号：US20230335201A1

公开(公告)日：2023-10-19

申请号：US18135915

申请日：2023-04-18

Applicant: Micron Technology, Inc.

Inventor： Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  David Scott Ebsen ,  Dung Viet Nguyen ,  Akira Goda

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/08

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.