公开(公告)号：US20240047362A1

公开(公告)日：2024-02-08

申请号：US17881308

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jiewei Chen ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe. Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230290721A1

公开(公告)日：2023-09-14

申请号：US17689527

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  Sijia Yu ,  Chieh Hsien Quek ,  Rita J. Klein ,  Nancy M. Lomeli

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230290409A1

公开(公告)日：2023-09-14

申请号：US17654311

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Jiewei Chen ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/76843

Abstract: A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230164957A1

公开(公告)日：2023-05-25

申请号：US17533225

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Tracy D. Evans ,  Gloria Y. Yang ,  Jiewei Chen ,  Jing Zhou

IPC: H05K7/20 ,  G05B15/02

CPC classification number: H05K7/20836 ,  G05B15/02

Abstract: Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

公开(公告)号：US11600630B2

公开(公告)日：2023-03-07

申请号：US16988156

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L27/11568 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220359391A1

公开(公告)日：2022-11-10

申请号：US17313814

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Jiewei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprises a stack structure comprising tiers of alternating conductive structures and insulative structures, staircase structures within the stack structure and including steps defined by edges of the tiers, contacts on the steps of the staircase structures, support pillars extending vertically through the stack structure, and support structures laterally adjacent to the contacts in a first horizontal direction and extending vertically through the stack structure. The support pillars exhibit a lateral dimension relatively larger than a lateral dimension of the contacts and the support structures. Related methods, memory devices, and systems are also described.

公开(公告)号：US20210125861A1

公开(公告)日：2021-04-29

申请号：US16667733

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jiewei Chen ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.