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1.
公开(公告)号:US20230397424A1
公开(公告)日:2023-12-07
申请号:US18324084
申请日:2023-05-25
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , Everett A. McTeer , Rita J. Klein , John D. Hopkins , Nancy M. Lomeli , Xiao Li , Christopher R. Ritchie , Alyssa N. Scarbrough , Jiewei Chen , Sijia Yu , Naiming Liu
Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.
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2.
公开(公告)号:US20240321741A1
公开(公告)日:2024-09-26
申请号:US18427720
申请日:2024-01-30
Applicant: Micron Technology, Inc.
Inventor: Zhou Xuan , Sijia Yu , Biow Hiem Ong
CPC classification number: H01L23/5283 , G11C16/0483 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprise a conductive structure and an insulative structure. The microelectronic device comprises a staircase structure having steps comprising lateral ends of the tiers, and contacts overlying the steps at different elevations of the staircase structure. The contacts comprise a liner material. The microelectronic device comprises conductive plug structures underlying the liner material of the contacts and comprising lateral portions within voids in at least some of the conductive structures, and vertical portions overlying the lateral portions. Related electronic systems and methods are also described.
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3.
公开(公告)号:US20230290721A1
公开(公告)日:2023-09-14
申请号:US17689527
申请日:2022-03-08
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , Jiewei Chen , Sijia Yu , Chieh Hsien Quek , Rita J. Klein , Nancy M. Lomeli
IPC: H01L23/522 , H01L23/532 , H01L27/11556 , H01L27/11582
CPC classification number: H01L23/5226 , H01L23/53257 , H01L23/53271 , H01L23/5329 , H01L27/11556 , H01L27/11582
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.
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