公开(公告)号：US20230164991A1

公开(公告)日：2023-05-25

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02 ,  H10B43/27 ,  H10B43/30

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/30625 ,  G11C16/0408 ,  G11C16/0466 ,  G11C5/025 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11600630B2

公开(公告)日：2023-03-07

申请号：US16988156

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L27/11568 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12250812B2

公开(公告)日：2025-03-11

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L21/306 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240332179A1

公开(公告)日：2024-10-03

申请号：US18615285

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Rajasekhar Venigalla ,  Justin David Shepherdson ,  Hiroaki Iuchi ,  Vladimir Samara

IPC: H01L23/528 ,  G11C16/04 ,  H01L21/768 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L21/76843 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: A method for making a vertical contact through levels of a memory device. A first liner is formed in an opening, and a second liner is formed over the first liner. The first liner is selectively removed from under the second liner to expose a first portion of the opening, such that the first liner remains intact over a second portion of the opening. The second liner is then removed, leaving the first liner overlying the second portion of the opening. A first portion of each of the layers of nitride materials in the first portion of the opening uncovered by the first liner is removed, the second portion of the first liner is removed, and a second portion of each of the layers of the nitride materials is removed in the second portion of the opening, wherein the second portion is less than the first portion.