公开(公告)号：US20190341378A1

公开(公告)日：2019-11-07

申请号：US16514159

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/683

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US10396052B2

公开(公告)日：2019-08-27

申请号：US15872845

申请日：2018-01-16

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G06F17/50

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

公开(公告)号：US10103134B2

公开(公告)日：2018-10-16

申请号：US15728123

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L29/40 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

公开(公告)号：US20180174993A1

公开(公告)日：2018-06-21

申请号：US15872845

申请日：2018-01-16

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  H01L25/065 ,  G06F17/50 ,  H01L25/00

CPC classification number: H01L24/17 ,  G06F17/5077 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11462 ,  H01L2224/1703 ,  H01L2224/17177 ,  H01L2224/17519

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

公开(公告)号：US09905527B1

公开(公告)日：2018-02-27

申请号：US15380877

申请日：2016-12-15

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G06F17/50

CPC classification number: H01L24/17 ,  G06F17/5077 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11462 ,  H01L2224/1703 ,  H01L2224/17177 ,  H01L2224/17519

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

公开(公告)号：US11955346B2

公开(公告)日：2024-04-09

申请号：US17227525

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/91 ,  H01L24/83 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26145 ,  H01L2224/29023 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/18161 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/27 ,  H01L2224/131 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US20210257226A1

公开(公告)日：2021-08-19

申请号：US17227525

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US11094684B2

公开(公告)日：2021-08-17

申请号：US16514159

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/683

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US11004697B2

公开(公告)日：2021-05-11

申请号：US16436461

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US20210074663A1

公开(公告)日：2021-03-11

申请号：US17102253

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G06F30/394

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.