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    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
    2.
    发明授权
    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权

    公开(公告)号：US09786612B2

    公开(公告)日：2017-10-10

    申请号：US15446583

    申请日：2017-03-01

    申请人： Micron Technology, Inc.

    发明人： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC分类号： H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/544

    CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
    4.
    发明授权
    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权
    处理晶圆级组件以减少翘曲的方法和相关组件

    公开(公告)号：US09589933B2

    公开(公告)日：2017-03-07

    申请号：US14312147

    申请日：2014-06-23

    申请人： Micron Technology, Inc.

    发明人： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC分类号： H01L21/78 ,  H01L25/065

    CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    摘要翻译： 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES
    6.
    发明申请
    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES 有权
    加工水平组合减少威胁的方法和相关组织

    公开(公告)号：US20150371969A1

    公开(公告)日：2015-12-24

    申请号：US14312147

    申请日：2014-06-23

    申请人： Micron Technology, Inc.

    发明人： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC分类号： H01L25/065 ,  H01L21/77

    CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    摘要翻译： 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING
    7.
    发明申请
    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING 有权

    公开(公告)号：US20210175194A1

    公开(公告)日：2021-06-10

    申请号：US17174827

    申请日：2021-02-12

    申请人： Micron Technology, Inc.

    发明人： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

    IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768

    摘要： A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

    Methods of making semiconductor devices
    8.
    发明授权
    Methods of making semiconductor devices 有权

    公开(公告)号：US10734370B2

    公开(公告)日：2020-08-04

    申请号：US16396235

    申请日：2019-04-26

    申请人： Micron Technology, Inc.

    发明人： Zhaohui Ma ,  Wei Zhou ,  Chee Chung So ,  Soo Loo Ang ,  Aibin Yu

    IPC分类号： H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

    摘要： Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.