公开(公告)号：US11152055B1

公开(公告)日：2021-10-19

申请号：US16934909

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/08 ,  G11C11/4094 ,  G11C7/12

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as isolation transistors and at least one precharge transistor, that are used to provide threshold voltage compensation.

公开(公告)号：US20210151092A1

公开(公告)日：2021-05-20

申请号：US16953015

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: G11C11/408 ,  G11C7/22 ,  G11C11/409 ,  G11C11/4074 ,  G11C11/4078

Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.

公开(公告)号：US20210057418A1

公开(公告)日：2021-02-25

申请号：US16543799

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US10586586B1

公开(公告)日：2020-03-10

申请号：US16183594

申请日：2018-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/408

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.

公开(公告)号：US12190939B2

公开(公告)日：2025-01-07

申请号：US18313948

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: G11C8/14 ,  G11C11/408 ,  G11C11/4097 ,  H01L29/423 ,  H10B12/00 ,  G11C8/08

Abstract: In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.

公开(公告)号：US12150289B2

公开(公告)日：2024-11-19

申请号：US17203236

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H10B12/00 ,  G11C5/06 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240079474A1

公开(公告)日：2024-03-07

申请号：US17903414

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H01L29/66 ,  H01L29/739

CPC classification number: H01L29/66348 ,  H01L29/7395

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include transistors formed from a plurality of semiconductor fins, and using a number of conductive lines passing through trenches between the fins to serve as a gate for the transistor.

公开(公告)号：US11877445B2

公开(公告)日：2024-01-16

申请号：US17150020

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Kyuseok Lee ,  Christopher G. Wieduwilt

IPC: H10N70/20 ,  H10B12/00 ,  H01L27/092 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/408 ,  G11C5/06

CPC classification number: H10B12/50 ,  G11C5/063 ,  G11C11/4085 ,  G11C11/4091 ,  H01L27/0924 ,  H01L29/785 ,  H10B12/36

Abstract: Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

公开(公告)号：US11832433B2

公开(公告)日：2023-11-28

申请号：US17526356

申请日：2021-11-15

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/50

Abstract: The present disclosure includes apparatuses and methods related to array and peripheral area masking. An example method comprises concurrently forming an array active area mask in an array active area and a peripheral component active area. The method further comprises forming a peripheral component active area mask in the peripheral component active area. The method further comprises concurrently forming etch stop spacers using the array active area mask in the array active area and the peripheral component active area. The method further comprises etching a portion of the peripheral component active area to open peripheral component conductive contact vias using the peripheral component active area mask together with the formed etch stop spacers in order to reduce over-etch of an opening to a device well while increasing surface area opening to a peripheral component conductive contact.

公开(公告)号：US20230274777A1

公开(公告)日：2023-08-31

申请号：US18313948

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: G11C11/408 ,  G11C11/4097 ,  H01L27/105 ,  H01L29/423

CPC classification number: G11C11/4085 ,  G11C11/4097 ,  H01L27/105 ,  H01L29/423 ,  G11C8/14

Abstract: In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.