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公开(公告)号：US11037613B2
公开(公告)日：2021-06-15
申请号：US16514431
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra
Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US20210020218A1
公开(公告)日：2021-01-21
申请号：US16514431
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra
IPC: G11C11/16
Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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Patent Agency Ranking
公开(公告)号：US10714177B2
公开(公告)日：2020-07-14
申请号：US16387234
申请日：2019-04-17
Applicant: Micron Technology, Inc.
Inventor： Mario Allegra , Mattia Boniardi
Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
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公开(公告)号：US10381075B2
公开(公告)日：2019-08-13
申请号：US15842504
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Totorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20180358094A1
公开(公告)日：2018-12-13
申请号：US16045526
申请日：2018-07-25
Applicant: Micron Technology, Inc.
Inventor： Mario Allegra , Mattia Boniardi
CPC classification number: G11C13/0069 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C2013/009 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1675
Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
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公开(公告)号：US10049737B2
公开(公告)日：2018-08-14
申请号：US15433881
申请日：2017-02-15
Applicant: Micron Technology, Inc.
Inventor： Mario Allegra , Mattia Boniardi
Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
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公开(公告)号：US20170236584A1
公开(公告)日：2017-08-17
申请号：US15433881
申请日：2017-02-15
Applicant: Micron Technology, Inc.
Inventor： Mario Allegra , Mattia Boniardi
CPC classification number: G11C13/0069 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C2013/009 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1675
Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
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