公开(公告)号：US11309285B2

公开(公告)日：2022-04-19

申请号：US16440328

申请日：2019-06-13

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US11189588B2

公开(公告)日：2021-11-30

申请号：US16236687

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

公开(公告)号：US20200258859A1

公开(公告)日：2020-08-13

申请号：US16270112

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L23/00

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

公开(公告)号：US10529659B2

公开(公告)日：2020-01-07

申请号：US16182901

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/528 ,  H01L23/532

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

公开(公告)号：US10261123B2

公开(公告)日：2019-04-16

申请号：US15685997

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle

IPC: G01R31/28 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  G01R31/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

公开(公告)号：US20190064257A1

公开(公告)日：2019-02-28

申请号：US15685997

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle

IPC: G01R31/28 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

公开(公告)号：US10141259B1

公开(公告)日：2018-11-27

申请号：US15852339

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/528 ,  H01L23/532

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

公开(公告)号：US08669179B2

公开(公告)日：2014-03-11

申请号：US13940034

申请日：2013-07-11

Applicant: Micron Technology, Inc.

Inventor： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC: H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20220208736A1

公开(公告)日：2022-06-30

申请号：US17697141

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US20220149014A1

公开(公告)日：2022-05-12

申请号：US17585392

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.