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21.发明授权公开(公告)号：US09075765B2
公开(公告)日：2015-07-07
申请号：US14029422
申请日：2013-09-17
Applicant: Micron Technology, Inc.
Inventor： William H. Radke , Victor Y. Tsai , James Cooke , Neal A. Galbo , Peter Feeley
CPC classification number: G06F13/102 , G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1684 , G06F13/4282 , G11C7/1045 , G11C7/22 , G11C7/222 , Y02D10/14 , Y02D10/151
Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
Abstract translation: 本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。 许多实施例包括以链式配置耦合到主机的主机和多个设备。 链接配置包括至少一个不直接耦合到主机的设备。 不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。
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公开(公告)号：US20140289505A1
公开(公告)日：2014-09-25
申请号：US14278510
申请日：2014-05-15
Applicant: Micron Technology, Inc.
Inventor： Neal A. Galbo , Victor Y. Tsai , William H. Radke , Krishnam R. Datla
IPC: G06F9/44
CPC classification number: G06F9/5077 , G06F3/062 , G06F3/0644 , G06F3/0679 , G06F9/4401 , G06F12/0246 , G06F2212/7206
Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
Abstract translation: 本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。 一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。 顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。
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公开(公告)号：US20140108678A1
公开(公告)日：2014-04-17
申请号：US14055436
申请日：2013-10-16
Applicant: Micron Technology, Inc.
Inventor： Peter Feeley , Robert N. Leibowitz , William H. Radke , Neal A. Galbo , Victor. Y. Tsai
IPC: G06F13/28
CPC classification number: G06F3/061 , G06F3/0659 , G06F3/0685 , G06F13/28 , G06F13/32 , G06F13/385 , G06F13/4282
Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
Abstract translation: 本公开包括用于控制存储器设备的方法，设备和系统。 用于控制存储器件实施例的一种方法包括将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中，在主机控制器中的寄存器中设置指向该命令的指针， 通过主机控制器更多的主机系统内存和主机控制器内存与存储设备; 并用存储器件执行命令。
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公开(公告)号：US20130275713A1
公开(公告)日：2013-10-17
申请号：US13868646
申请日：2013-04-23
Applicant: Micron Technology, Inc.
Inventor： Neal A. Galbo , Victor Y. Tsai , William H. Radke , Krishnam R. Datla
IPC: G06F9/50
CPC classification number: G06F9/5077 , G06F3/062 , G06F3/0644 , G06F3/0679 , G06F9/4401 , G06F12/0246 , G06F2212/7206
Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
Abstract translation: 本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。 一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。 顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。
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公开(公告)号：US20230054662A1
公开(公告)日：2023-02-23
申请号：US17981703
申请日：2022-11-07
Applicant: Micron Technology, Inc.
Inventor： Victor Y. Tsai , Danilo Caraccio , Daniele Balluchi , Neal A. Galbo , Robert Warren
IPC: G06F3/06
Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
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Patent Agency Ranking
公开(公告)号：US20210019052A1
公开(公告)日：2021-01-21
申请号：US17061991
申请日：2020-10-02
Applicant: Micron Technology, Inc.
Inventor： Neal A. Galbo
IPC: G06F3/06
Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.
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公开(公告)号：US10884661B2
公开(公告)日：2021-01-05
申请号：US16207453
申请日：2018-12-03
Applicant: Micron Technology, Inc.
Inventor： Victor Y. Tsai , Danilo Caraccio , Daniele Balluchi , Neal A. Galbo , Robert Warren
IPC: G06F3/06
Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
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公开(公告)号：US10795576B2
公开(公告)日：2020-10-06
申请号：US16177985
申请日：2018-11-01
Applicant: Micron Technology, Inc.
Inventor： Neal A. Galbo
IPC: G06F3/06
Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.
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公开(公告)号：US09929967B2
公开(公告)日：2018-03-27
申请号：US14108599
申请日：2013-12-17
Applicant: Micron Technology, Inc.
Inventor： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC: H04L12/801 , H04L12/807 , H04L29/08 , H04L1/18
CPC classification number: H04L47/34 , H04L1/1867 , H04L47/27 , H04L69/324
Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
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公开(公告)号：US09588697B2
公开(公告)日：2017-03-07
申请号：US14718461
申请日：2015-05-21
Applicant: Micron Technology, Inc.
Inventor： Peter Feeley , Robert N. Leibowitz , William H. Radke , Neal A. Galbo , Victor Y. Tsai
CPC classification number: G06F3/061 , G06F3/0659 , G06F3/0685 , G06F13/28 , G06F13/32 , G06F13/385 , G06F13/4282
Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
Abstract translation: 本公开包括用于控制存储器设备的方法，设备和系统。 用于控制存储器件实施例的一种方法包括将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中，在主机控制器中的寄存器中设置指向该命令的指针， 通过主机控制器更多的主机系统内存和主机控制器内存与存储设备; 并用存储器件执行命令。
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