公开(公告)号：US20230048133A1

公开(公告)日：2023-02-16

申请号：US17400935

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Luigi Esposito ,  Alberto Sassara ,  Paolo Papa ,  Massimo Iaculo

IPC: G06F3/06

Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

公开(公告)号：US20230041215A1

公开(公告)日：2023-02-09

申请号：US17397733

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Paolo Papa ,  Crescenzo Attanasio

IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/10

Abstract: Methods, systems, and devices for power management techniques are described. A memory system may receive a command to exit a first power mode and enter a second power mode. The first power mode may have a lower power consumption than the second power mode. The memory system may determine whether a duration of an idle period associated with the first power mode satisfies a threshold based on receiving the command to exit the first power mode. The memory system may receive another command associated with executing a flush operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.

公开(公告)号：US20220237080A1

公开(公告)日：2022-07-28

申请号：US17645180

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Crescenzo Attanasio ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Paolo Papa ,  Antonio Eliso

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.

公开(公告)号：US20220084572A1

公开(公告)日：2022-03-17

申请号：US17532364

申请日：2021-11-22

Applicant: Micron Technology Inc.

Inventor： Luca Porzio ,  Marco Di Pasqua ,  Paolo Papa

IPC: G11C8/00 ,  G11C29/00 ,  G06F11/07 ,  G06F12/02

Abstract: A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.

公开(公告)号：US20220027284A1

公开(公告)日：2022-01-27

申请号：US17494740

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US20250061021A1

公开(公告)日：2025-02-20

申请号：US18814142

申请日：2024-08-23

Applicant: Micron Technology, Inc.

Inventor： Crescenzo Attanasio ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Paolo Papa ,  Antonio Eliso

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

Abstract: Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.

公开(公告)号：US11907556B2

公开(公告)日：2024-02-20

申请号：US17580296

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara ,  Carminantonio Manganelli ,  Salvatore Del Prete

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F12/0246 ,  G06F12/0646 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/7205

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

公开(公告)号：US20230367478A1

公开(公告)日：2023-11-16

申请号：US18137820

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0679 ,  G06F3/0655

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

公开(公告)号：US11650931B2

公开(公告)日：2023-05-16

申请号：US17234062

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US11521690B2

公开(公告)日：2022-12-06

申请号：US16488681

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Paolo Papa ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  H03K19/21

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.