公开(公告)号：US20170358339A1

公开(公告)日：2017-12-14

申请号：US15676608

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US09786347B1

公开(公告)日：2017-10-10

申请号：US15071490

申请日：2016-03-16

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US12158826B2

公开(公告)日：2024-12-03

申请号：US17853321

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G11C11/22 ,  G11C29/12 ,  G11C29/36 ,  G11C29/44 ,  G11C29/52 ,  G06F11/10 ,  G11C29/42

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US11238913B2

公开(公告)日：2022-02-01

申请号：US16806858

申请日：2020-03-02

Applicant: Micron Technology, inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20210005239A1

公开(公告)日：2021-01-07

申请号：US16893304

申请日：2020-06-04

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US10559339B2

公开(公告)日：2020-02-11

申请号：US16189416

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C5/10 ,  G11C11/22 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/11507 ,  H01L23/528 ,  G11C11/408 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C5/06

Abstract: Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.

公开(公告)号：US10535397B1

公开(公告)日：2020-01-14

申请号：US16107280

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/408 ,  G11C11/4076 ,  G11C7/08 ,  G11C11/4097 ,  H01L27/108

Abstract: Techniques are provided for sensing a memory cell configured to store three or more states. A charge may be transferred between a digit line and a node coupled with a sense component using a charge transfer device. During a single read operation, multiple voltages may be applied to the gate of the charge transfer device. The node may be sensed a number of times based on a number of voltages applied to the gate of the charge transfer device. The charge may be transferred by the charge transfer device based on a value of the signal on a digit line and a voltage applied to the gate of the charge transfer device. Based on the charge being transferred and the sense component sensing the node multiple times, a logic state associated with the memory cell may be determined.

公开(公告)号：US10311934B2

公开(公告)日：2019-06-04

申请号：US15692994

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US20180226116A1

公开(公告)日：2018-08-09

申请号：US15426871

申请日：2017-02-07

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

公开(公告)号：US20180144783A1

公开(公告)日：2018-05-24

申请号：US15858747

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.