公开(公告)号：US11152509B2

公开(公告)日：2021-10-19

申请号：US16826011

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11597 ,  H01L29/10 ,  H01L27/11514 ,  H01L29/08

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US11107817B2

公开(公告)日：2021-08-31

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11038027B2

公开(公告)日：2021-06-15

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US10998440B2

公开(公告)日：2021-05-04

申请号：US16596407

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Ramanathan Gandhi ,  Hong Li ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Sanh D. Tang ,  Scott E. Sills

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

公开(公告)号：US20200161295A1

公开(公告)日：2020-05-21

申请号：US16748269

申请日：2020-01-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kurt D. Beigel

IPC: H01L27/06 ,  G11C7/10 ,  G11C8/08 ,  H01L27/12 ,  G11C29/44 ,  H01L21/822 ,  G11C7/06 ,  G11C8/10 ,  G11C7/12 ,  H01L23/528

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described.

公开(公告)号：US20200013955A1

公开(公告)日：2020-01-09

申请号：US16552745

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Christopher W. Petz ,  Yongjun Jeff Hu ,  Scott E. Sills ,  D. V. Nirmal Ramaswamy

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L27/22 ,  C23C14/06 ,  C23C14/08 ,  C23C14/18 ,  C23C14/34 ,  C23C16/34 ,  C23C16/36 ,  C23C16/40 ,  C23C16/455

Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.

公开(公告)号：US10355002B2

公开(公告)日：2019-07-16

申请号：US15667159

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L49/02 ,  H01L27/108 ,  H01L21/768 ,  H01L27/11507

Abstract: A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.

公开(公告)号：US20190206449A1

公开(公告)日：2019-07-04

申请号：US16203321

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: G11C5/02 ,  H01L21/822 ,  H01L29/66 ,  H01L27/02 ,  H01L29/786 ,  H03K19/0948 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/308 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08 ,  G11C29/44 ,  G11C7/06 ,  G11C5/14

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

公开(公告)号：US20190067437A1

公开(公告)日：2019-02-28

申请号：US16118064

申请日：2018-08-30

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact include a conductive material, such as Ruthenium, to reduce the Schottky effects at the interface with the channel material.

公开(公告)号：US10153196B1

公开(公告)日：2018-12-11

申请号：US15686082

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L45/00 ,  H01L21/762 ,  G11C8/12 ,  H01L27/11502 ,  H01L27/24 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/11585

Abstract: Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.