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公开(公告)号：US08817472B2
公开(公告)日：2014-08-26
申请号：US13158802
申请日：2011-06-13
申请人： Sam Ziqun Zhao , Milind S. Bhagavat
发明人： Sam Ziqun Zhao , Milind S. Bhagavat
CPC分类号： H01L23/36 , H01L23/467 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73257 , H01L2924/15311 , H05K7/20172 , H01L2924/00014 , H01L2924/00
摘要： An apparatus for cooling a semiconductor element is provided. The apparatus can include an electron emitter configured to emit electrons such that at least some of the emitted electrons become attached to air particulates and an air accelerator configured to generate an electric field that accelerates the air particulates toward the air accelerator to create an air flow over at least a portion of the semiconductor element. The air flow carries heat away from the at least a portion of the semiconductor element.
摘要翻译： 提供一种用于冷却半导体元件的装置。 该装置可以包括被配置为发射电子的电子发射器，使得发射的电子中的至少一些变得附着到空气微粒，并且空气加速器被配置成产生电场，该空气加速空气微粒朝向空气加速器以产生空气流 半导体元件的至少一部分。 空气流从半导体元件的至少一部分携带热量。
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22.发明申请公开(公告)号：US20110101504A1
公开(公告)日：2011-05-05
申请号：US12899262
申请日：2010-10-06
CPC分类号： B24B7/228 , B24B7/17 , B24B37/08 , B24B37/28 , B24B41/061
摘要： Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.
摘要翻译： 本文公开了用静压垫保持工件的方法。 衬垫包括形成在与晶片直接相对的身体的表面中的静水压凹坑。 凹穴适于接收流体通过主体并进入凹穴，以在主体面和工件之间提供阻挡物，同时在研磨期间仍然施加压力以保持工件。 静压垫允许晶片相对于垫围绕其公共轴线旋转。 当砂轮相对于静液压垫移动或倾斜时，袋被定向成减小在晶片中产生的流体静力弯矩，有助于防止通常由砂轮的移动和倾斜引起的晶片表面的纳米拓扑降解。
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公开(公告)号：US20200035606A1
公开(公告)日：2020-01-30
申请号：US16048826
申请日：2018-07-30
申请人： Milind S. Bhagavat , Lei Fu , Farshad Ghahghahi
发明人： Milind S. Bhagavat , Lei Fu , Farshad Ghahghahi
IPC分类号： H01L23/538 , H01L23/00 , H01L25/16 , H01L23/31 , H01L25/065 , H01L21/48 , H01L21/56 , H01L25/00 , H01L21/683
摘要： Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
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公开(公告)号：US20200006280A1
公开(公告)日：2020-01-02
申请号：US16023399
申请日：2018-06-29
申请人： Priyal Shah , Milind S. Bhagavat
发明人： Priyal Shah , Milind S. Bhagavat
IPC分类号： H01L23/00
摘要： Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.
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公开(公告)号：US10431517B2
公开(公告)日：2019-10-01
申请号：US15686558
申请日：2017-08-25
申请人： John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
发明人： John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
IPC分类号： H01L23/367 , H01L25/00 , H01L25/065 , H01L23/36 , H01L23/373
摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
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公开(公告)号：US20120050989A1
公开(公告)日：2012-03-01
申请号：US13173456
申请日：2011-06-30
IPC分类号： H05K7/20
CPC分类号： H01L23/467 , H01L23/3675 , H01L2924/0002 , H05K7/20136 , H05K7/20145 , H05K7/20154 , H01L2924/00
摘要： Methods, systems, and apparatuses are described for cooling electronic devices. The electrical device includes an integrated circuit die (IC) having opposing first and second surfaces, a plurality of interconnects on the second surface of the IC die that enable the IC die to be coupled to a substrate, and a flexural plate wave device. The flexural plate wave device is configured to generate a stream of air to flow across the electrical device to cool the IC die during operation of the IC die.
摘要翻译： 描述了用于冷却电子设备的方法，系统和装置。 电气装置包括具有相对的第一和第二表面的集成电路管芯（IC），IC模头的第二表面上的使得IC管芯能够耦接到衬底的多个互连件，以及弯曲板形波装置。 弯曲板波装置被配置为产生流过电气装置的空气流，以在IC管芯的工作期间冷却IC管芯。
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27.发明授权Method for assessing workpiece nanotopology using a double side wafer grinder 有权使用双面晶圆研磨机评估工件纳米拓扑的方法公开(公告)号：US07927185B2
公开(公告)日：2011-04-19
申请号：US12631929
申请日：2009-12-07
IPC分类号： B24B49/00
摘要： A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance.
摘要翻译： 使用将晶片保持在具有一对砂轮的平面中的类型的双面研磨机和一对静压垫来处理半导体晶片的方法。 该方法包括测量晶片与至少一个传感器之间的距离并使用所测量的距离来确定晶片纳米拓扑。 确定包括使用处理器基于测量的距离来执行晶片的有限元结构分析。
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28.发明授权公开(公告)号：US07662023B2
公开(公告)日：2010-02-16
申请号：US11617430
申请日：2006-12-28
IPC分类号： B24B49/00
摘要： A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.
摘要翻译： 双面研磨机包括一对砂轮和一对静压垫，其可操作以保持平坦工件（例如，半导体晶片），使得工件的一部分位于砂轮之间并且部分工件位于静水压 垫 至少一个传感器测量工件和相应传感器之间的距离，用于评估工件的纳米拓扑学。 在本发明的方法中，在研磨期间测量与工件的距离，并用于评估工件的纳米拓扑学。 例如，可以使用传感器数据来执行工件的有限元结构分析以导出至少一个边界条件。 纳米技术评估可以在从研磨机上取出工件之前开始，提供快速的纳米拓扑反馈。 可以使用空间滤波器来进一步处理后预测工件的可能纳米拓扑。
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29.发明申请公开(公告)号：US20100087123A1
公开(公告)日：2010-04-08
申请号：US12631929
申请日：2009-12-07
摘要： A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance.
摘要翻译： 使用将晶片保持在具有一对砂轮的平面中的类型的双面研磨机和一对静压垫来处理半导体晶片的方法。 该方法包括测量晶片与至少一个传感器之间的距离并使用所测量的距离来确定晶片纳米拓扑。 确定包括使用处理器基于测量的距离来执行晶片的有限元结构分析。
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30.发明授权Method of estimating post-polishing waviness characteristics of a semiconductor wafer 失效估计半导体晶片的后抛光波纹特性的方法公开(公告)号：US06613591B1
公开(公告)日：2003-09-02
申请号：US10092479
申请日：2002-03-07
IPC分类号： H01L2100
CPC分类号： B24B37/005 , B24B37/042 , B24B49/00
摘要： A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.
摘要翻译： 一种用于在抛光之前基于精确测量晶片在切割条件下的波纹度来估计抛光后晶片的可能波纹度的方法。 该方法测量上下晶片表面的厚度分布，以在切线方向上构建晶片的中间轮廓。 然后将中间表面通过适当的高斯滤波器，使得所得轮廓的翘曲估计晶片在后抛光阶段是否将呈现不可接受的波纹。
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