公开(公告)号：US08617936B2

公开(公告)日：2013-12-31

申请号：US12819607

申请日：2010-06-21

Applicant: Munaf Rahimo ,  Babak H-Alikhani

Inventor： Munaf Rahimo ,  Babak H-Alikhani

IPC: H01L21/332

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/41708 ,  H01L29/66333

Abstract: A method for manufacturing a reverse-conducting semiconductor device (RC-IGBT) with a seventh layer formed as a gate electrode and a first electrical contact on a emitter side and a second electrical contact on a collector side, which is opposite the emitter side, a wafer of a first conductivity type with a first side and a second side opposite the first side is provided. For the manufacturing of the RC-IGBT on the collector side, a first layer of the first conductivity type or of a second conductivity type is created on the second side. A mask with an opening is created on the first layer and those parts of the first layer, on which the opening of the mask is arranged, are removed. The remaining parts of the first layer form a third layer. Afterwards, for the manufacturing of a second layer of a different conductivity type than the third layer, ions are implanted into the wafer on the second side into those parts of the wafer, on which the at least one opening is arranged. Then the mask is removed and an annealing for the activation of the second layer is performed and a second electrical contact, which is in direct electrical contact to the second and third layer, is created on the second side.

Abstract translation: 一种制造反向导电半导体器件（RC-IGBT）的方法，其具有形成为栅电极的第七层和发射极侧的第一电接触和与发射极侧相反的集电极侧的第二电接触， 提供具有第一侧和与第一侧相对的第二侧的第一导电类型的晶片。 为了在集电极侧制造RC-IGBT，在第二侧产生第一导电类型或第二导电类型的第一层。 在第一层上形成具有开口的掩模，并且去除其上布置有掩模开口的第一层的那些部分。 第一层的其余部分形成第三层。 之后，为了制造不同于第三层的不同导电类型的第二层，将离子注入第二侧的晶片进入晶片的其中布置有至少一个开口的部分。 然后去除掩模，并执行用于激活第二层的退火，并且在第二侧上产生与第二和第三层直接电接触的第二电接触。

公开(公告)号：US08501586B2

公开(公告)日：2013-08-06

申请号：US11812030

申请日：2007-06-14

Applicant: Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

Inventor： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

Abstract translation: 为了产生用于在高阻挡电压下操作的功率半导体，在具有掺杂第一电荷载体类型的相同电荷载流子型的中等掺杂层的轻掺杂层上产生。 在远离轻掺杂层的介质掺杂层的该侧产生高掺杂层，其中高掺杂层保留在最终半导体中的具有高掺杂的部分形成第二阻挡层，其中掺杂 高掺杂层比掺杂中掺杂层高。 随后将电极扩散到高掺杂层中。 保留在成品半导体中的低掺杂部分形成漂移层，剩余的中等掺杂部分形成第一停止层。

公开(公告)号：US08450793B2

公开(公告)日：2013-05-28

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。

公开(公告)号：US08435863B2

公开(公告)日：2013-05-07

申请号：US12819646

申请日：2010-06-21

Applicant: Munaf Rahimo ,  Wolfgang Janisch ,  Eustachio Faggiano

Inventor： Munaf Rahimo ,  Wolfgang Janisch ,  Eustachio Faggiano

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L27/0664 ,  H01L29/0834 ,  H01L29/41708 ,  H01L29/66333 ,  H01L29/7395

Abstract: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A first layer of a first conductivity type is created on a collector side before a second layer of a second conductivity type is created on the collector side. An electrical contact in direct electrical contact with the first and second layers is created on the collector side. A shadow mask is applied on the collector side, and a third layer of the first conductivity type is created through the shadow mask. At least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The island is used as a mask for creating the second layer, and those parts of the third layer which are covered by the island form the second layer.

Abstract translation: 提供了包括续流二极管和绝缘栅双极晶体管（IGBT）的反向导电半导体器件（RC-IGBT）以及制造RC-IGBT的方法。 在集电器侧产生第二导电类型的第二层之前，在集电极侧产生第一导电类型的第一层。 在集电器侧产生与第一和第二层直接电接触的电接触。 在收集器侧施加荫罩，通过荫罩产生第一导电类型的第三层。 通过荫罩产生至少一个作为最终RC-IGBT中的第二电接触部分的导电岛。 岛用作创建第二层的掩模，并且被岛覆盖的第三层的那些部分形成第二层。

公开(公告)号：US08212283B2

公开(公告)日：2012-07-03

申请号：US12770451

申请日：2010-04-29

Applicant: Liutauras Storasta ,  Munaf Rahimo ,  Christoph Von Arx ,  Arnost Kopta ,  Raffael Schnell

Inventor： Liutauras Storasta ,  Munaf Rahimo ,  Christoph Von Arx ,  Arnost Kopta ,  Raffael Schnell

IPC: H01L29/739

CPC classification number: H01L29/0834 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

Abstract: A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e., larger) than two times the base layer thickness; the at least one second region is that part of the second layer, which is not the at least one third region; the at least one third region is arranged in the central part of the active region in such a way that there is a minimum distance between the third region border to the active region border of at least once the base layer thickness; the sum of the areas of the at least one third region is between 10 and 30% of the active region; and each first region width is smaller than the base layer thickness.

Abstract translation: 公开了具有电活性区域的反向导电半导体器件，其包括在同一晶片上的续流二极管和绝缘栅双极晶体管。 晶片的一部分形成具有基层厚度的基底层。 具有至少一个第一区域和第二导电类型的具有至少一个第二和第三区域的第一导电类型的第一层交替地布置在集电极侧。 每个区域具有由区域边界包围的区域宽度的区域区域。 RC-IGBT可以被配置为使得满足以下示例性几何规则：每个第三区域区域是任何两个第一区域具有比基底层厚度的两倍大的距离（即，更大）的区域; 所述至少一个第二区域是所述第二层的不是所述至少一个第三区域的部分; 至少一个第三区域被布置在有源区域的中心部分中，使得在至少一次基底层厚度的第三区域边界与有源区域边界之间存在最小距离; 所述至少一个第三区域的面积之和为有效区域的10％至30％; 并且每个第一区域宽度小于基底层厚度。

公开(公告)号：US07989878B2

公开(公告)日：2011-08-02

申请号：US11979454

申请日：2007-11-02

Applicant: Munaf Rahimo

Inventor： Munaf Rahimo

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/0696 ,  H01L29/7395

Abstract: An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced safe operating are capability. The additional well regions (11) outside the active cell (5) do not affect the active cell design in terms of cell pitch, i.e. the design rules for cell spacing, and hole drainage between the cells, hence resulting in optimum carrier profile at the emitter side for low on-state losses.

Abstract translation: 一种具有活动电池（5）的n沟道绝缘栅极半导体器件，包括由n型第三层（8）围绕的ap沟道阱区（6），该器件还包括邻近沟道阱形成的附加阱区（11） 活性半导体电池（5）外部的区域（6）具有增强的安全运行能力。 在活性细胞（5）外部的附加阱区（11）在细胞间距方面不影响活性细胞设计，即细胞间隔的设计规则和细胞之间的孔引流，因此导致最佳的载体谱 发射极侧为低导通状态损耗。

公开(公告)号：US20110108953A1

公开(公告)日：2011-05-12

申请号：US12942410

申请日：2010-11-09

Applicant: Jan VOBECKY ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

Inventor： Jan VOBECKY ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

IPC: H01L29/00 ,  H01L21/22

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm−3 and 2*1017 cm−3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 μm. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm−3 and 1*1015 cm−3 is reached between a first depth, which is at least 20 μm, and a second depth, which is at maximum 50 μm. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers.

Abstract translation: 快速恢复二极管包括具有阴极侧和与阴极侧相对的阳极侧的n掺杂基极层。 p型掺杂阳极层设置在阳极侧。 阳极层具有掺杂分布并且包括至少两个子层。 第一个子层具有第一最大掺杂浓度，其在2×1016cm-3和2×1017cm-3之间，并且高于任何其它子层的最大掺杂浓度。 最后一个子层具有比任何其他子层深度大的最后一个子层深度。 最后的子层深度为90〜120μm。 阳极层的掺杂分布下降，使得在第一深度（至少20μm）和第二深度之间达到在5×10 14 cm -3和1×10 15 cm -3范围内的掺杂浓度，其中 最大为50μm。 通过使用铝扩散层作为至少两个子层来实现掺杂浓度的这种分布。

公开(公告)号：US20100244093A1

公开(公告)日：2010-09-30

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。

公开(公告)号：US08508016B2

公开(公告)日：2013-08-13

申请号：US13160945

申请日：2011-06-15

Applicant: Munaf Rahimo ,  Ulrich Schlapbach ,  Arnost Kopta

Inventor： Munaf Rahimo ,  Ulrich Schlapbach ,  Arnost Kopta

IPC: H01L29/66

CPC classification number: H01L29/0834 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/861

Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 μm and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 μm.

Abstract translation: 双极穿通半导体器件具有至少包括两层结构的半导体衬底，具有第一电接触的第一主侧和具有第二电接触的第二主侧。 两层结构中的一层是第一导电类型的基层。 第一导电类型的缓冲层布置在基层上。 第一层包括交替的第一导电类型的第一区域和第二导电类型的第二区域。 第一层布置在缓冲层和第二电接触之间。 第二区域是深度为最大2μm的激活区域和掺杂分布，其从最大掺杂浓度的90％下降到最多1um的10％。

公开(公告)号：US08461622B2

公开(公告)日：2013-06-11

申请号：US13098827

申请日：2011-05-02

Applicant: Arnost Kopta ,  Munaf Rahimo

Inventor： Arnost Kopta ,  Munaf Rahimo

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width. Each first pilot region width is equal to or larger than two times the base layer thickness, and the sum of the areas of the second pilot regions is larger than the sum of the areas of the first pilot regions.

Abstract translation: 反向导电半导体器件包括在同一晶片上的续流二极管和绝缘栅双极晶体管（IGBT）。 晶片的一部分形成具有基层厚度的基底层。 IGBT包括布置在晶片的相对侧上的集电极侧和发射极侧。 第一导电类型的第一层和第二导电类型的第二层交替地布置在集电极侧。 第一层包括具有第一区域宽度的至少一个第一区域和具有第一引导区域宽度的至少一个第一引导区域。 第二层包括具有第二区域宽度的至少一个第二区域和具有第二导频区域宽度的至少一个第二导频区域。 每个第二区域宽度等于或大于基底层厚度，而每个第一区域宽度小于基底层厚度。 每个第二导频区宽度大于每个第一导频区宽度。 每个第一导频区宽度等于或大于基层厚度的两倍，并且第二导频区域的面积之和大于第一导频区域的面积之和。