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    Power semiconductor
    1.
    发明申请
    Power semiconductor 有权
    功率半导体

    公开(公告)号：US20070281442A1

    公开(公告)日：2007-12-06

    申请号：US11812030

    申请日：2007-06-14

    申请人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    发明人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    IPC分类号： H01L21/30

    CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

    摘要： In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

    摘要翻译： 为了产生用于在高阻挡电压下操作的功率半导体，在具有掺杂第一电荷载体类型的相同电荷载流子型的中等掺杂层的轻掺杂层上产生。 在远离轻掺杂层的介质掺杂层的该侧产生高掺杂层，其中高掺杂层保留在最终半导体中的具有高掺杂的部分形成第二阻挡层，其中掺杂 高掺杂层比掺杂中掺杂层高。 随后将电极扩散到高掺杂层中。 保留在成品半导体中的低掺杂部分形成漂移层，剩余的中等掺杂部分形成第一停止层。

    Power semiconductor
    2.
    发明授权
    Power semiconductor 有权
    功率半导体

    公开(公告)号：US08501586B2

    公开(公告)日：2013-08-06

    申请号：US11812030

    申请日：2007-06-14

    申请人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    发明人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

    摘要： In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

    摘要翻译： 为了产生用于在高阻挡电压下操作的功率半导体，在具有掺杂第一电荷载体类型的相同电荷载流子型的中等掺杂层的轻掺杂层上产生。 在远离轻掺杂层的介质掺杂层的该侧产生高掺杂层，其中高掺杂层保留在最终半导体中的具有高掺杂的部分形成第二阻挡层，其中掺杂 高掺杂层比掺杂中掺杂层高。 随后将电极扩散到高掺杂层中。 保留在成品半导体中的低掺杂部分形成漂移层，剩余的中等掺杂部分形成第一停止层。

    Igbt cathode design with improved safe operating area capability
    3.
    发明申请
    Igbt cathode design with improved safe operating area capability 有权
    Igbt阴极设计，具有改进的安全操作区域能力

    公开(公告)号：US20070158686A1

    公开(公告)日：2007-07-12

    申请号：US10579837

    申请日：2004-11-16

    申请人： Munaf Rahimo ,  Stefan Linder

    发明人： Munaf Rahimo ,  Stefan Linder

    IPC分类号： H01L31/00 ,  H01L29/739

    CPC分类号： B67D1/1422 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

    摘要： In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

    摘要翻译： 在绝缘栅双极晶体管中，根据本发明，通过包括设置在沟道区域（7）中的第一基极区域（81）的双折叠基极区域实现改进的安全工作面积能力，使得其包围 一个或多个源极区域（6），但不与栅极氧化物层（41）下面的第二主表面相邻，并且第二基极区域（82）设置在基极接触区域（821）下面的半导体衬底 ），使得其与沟道区域（7）和第一基极区域（81）部分重叠。

    IGBT cathode design with improved safe operating area capability
    4.
    发明授权
    IGBT cathode design with improved safe operating area capability 有权
    IGBT阴极设计，具有改进的安全操作面积能力

    公开(公告)号：US07446376B2

    公开(公告)日：2008-11-04

    申请号：US10579837

    申请日：2004-11-16

    申请人： Munaf Rahimo ,  Stefan Linder

    发明人： Munaf Rahimo ,  Stefan Linder

    IPC分类号： H01L29/66

    CPC分类号： B67D1/1422 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

    摘要： In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

    摘要翻译： 在绝缘栅双极晶体管中，根据本发明，通过包括设置在沟道区域（7）中的第一基极区域（81）的双折叠基极区域实现改进的安全工作面积能力，使得其包围 一个或多个源极区域（6），但不与栅极氧化物层（41）下面的第二主表面相邻，并且第二基极区域（82）设置在基极接触区域（821）下面的半导体衬底 ），使得其与沟道区域（7）和第一基极区域（81）部分重叠。

    Connection arrangement for semiconductor power modules
    6.
    发明授权
    Connection arrangement for semiconductor power modules 有权
    半导体电源模块的连接布置

    公开(公告)号：US09024421B2

    公开(公告)日：2015-05-05

    申请号：US13096155

    申请日：2011-04-28

    申请人： Didier Cottet ,  Gunnar Asplund ,  Stefan Linder

    发明人： Didier Cottet ,  Gunnar Asplund ,  Stefan Linder

    IPC分类号： H01L23/02 ,  H01L25/07

    CPC分类号： H01L25/072 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

    摘要翻译： 半导体功率模块包括至少两个子模块。 子模块包括至少一个具有集电极，发射极和栅极的相应晶体管。 所述模块包括具有用于将所述至少两个子模块的集电极连接到外部电路部件的集电极端子单元的连接装置，至少两个用于将所述至少两个子模块的各个发射极分别连接到外部电路的发射极端子单元 以及用于将至少两个子模块的各个门单独地连接到外部电路部件的至少两个栅极端子单元。

    Power semiconductor module
    7.
    发明授权
    Power semiconductor module 有权
    功率半导体模块

    公开(公告)号：US06738258B2

    公开(公告)日：2004-05-18

    申请号：US10302824

    申请日：2002-11-25

    申请人： Bo Bijlenga ,  Fabian Zwick ,  Stefan Linder ,  Patrick Erne

    发明人： Bo Bijlenga ,  Fabian Zwick ,  Stefan Linder ,  Patrick Erne

    IPC分类号： H05K720

    CPC分类号： H01L24/72 ,  H01L25/115 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/00

    摘要： The power semiconductor module (1) comprises a housing (5), a covering panel (11) and at least two submodules (21, 22). The submodules (21, 22) each comprise at least one semiconductor chip, which has two main electrodes which are electrically conductively connected to main connections (3, 4) of the submodules. The submodules (21, 22) are arranged alongside one another, and one of their two main surfaces is pressed against the covering panel (11) of the module. The submodules are electrically connected in series. The maximun blocking voltage of the module is doubled by connecting the submodules, which are arranged alongside one another, in series. This reduces the length and the costs of the stack for hihg-voltage switch since fewer components are required for the same blocking voltages, in particular fewer modules and cooling elements.

    摘要翻译： 功率半导体模块（1）包括壳体（5），覆盖板（11）和至少两个子模块（21,22）。 子模块（21,22）各自包括至少一个半导体芯片，其具有导电连接到子模块的主连接（3,4）的两个主电极。 子模块（21,22）彼此并排布置，并且其两个主表面中的一个压靠在模块的覆盖板（11）上。 子模块串联电连接。 通过连接彼此并排布置的子模块将模块的最大阻断电压加倍。 这减少了用于高压开关的堆叠的长度和成本，因为对于相同的阻挡电压，特别是较少的模块和冷却元件需要更少的部件。

    Process for fabricating a semiconductor component
    8.
    发明授权
    Process for fabricating a semiconductor component 失效
    半导体部件的制造方法

    公开(公告)号：US06475876B2

    公开(公告)日：2002-11-05

    申请号：US09374844

    申请日：1999-08-16

    申请人： Norbert Galster ,  Stefan Linder

    发明人： Norbert Galster ,  Stefan Linder

    IPC分类号： H01L2130

    CPC分类号： H01L29/6609 ,  H01L29/8611

    摘要： In a process for fabricating a semiconductor component, in particular a semiconductor diode, a semiconductor substrate (1) is provided with metal layers (3, 4) in order to form electrode terminals and with passivation (2), and is exposed to particle irradiation (P) in order to adjust the carrier lifetime. This being the case, at least the metal layer (3) on the irradiation side and the passivation (2) are not applied until after the particle irradiation (P). As a result, a continuous defect region (5), which precludes undesired edge effects, is obtained in the semiconductor substrate (1).

    摘要翻译： 在制造半导体部件，特别是半导体二极管的工艺中，半导体衬底（1）设置有金属层（3,4）以形成电极端子和钝化层（2），并暴露于粒子照射 （P），以调整载体寿命。 在这种情况下，至少在照射侧的金属层（3）和钝化层（2）直到粒子照射（P）才被施加。 结果，在半导体衬底（1）中获得了排除不想要的边缘效应的连续缺陷区域（5）。

    Gate turn-off thyristor with stop layer
    9.
    发明授权
    Gate turn-off thyristor with stop layer 失效
    门极关断晶闸管与停止层

    公开(公告)号：US6107651A

    公开(公告)日：2000-08-22

    申请号：US124892

    申请日：1998-07-30

    申请人： Stefan Linder ,  Andre Weber

    发明人： Stefan Linder ,  Andre Weber

    IPC分类号： H01L29/74 ,  H01L29/08 ,  H01L29/744

    CPC分类号： H01L29/0834 ,  H01L29/0839 ,  H01L29/744

    摘要： In a gate turn-off thyristor (GTO) with homogeneous anode, emitter and stop layer, a device which short-circuit the stop layer with the anode is provided in an edge termination region. As a result, in a reverse-biased state, the GTO has a structure of a diode in the edge region and amplification of a reverse current is obviated. With this structure, thermal loading in the edge region is reduced, as the GTO tolerates a higher operating temperature at a predetermined voltage.

    摘要翻译： 在具有均匀的阳极，发射极和停止层的栅极截止晶闸管（GTO）中，在边缘终止区域中提供了一个使阳极与止动层短路的装置。 结果，在反向偏置状态下，GTO具有边缘区域中的二极管的结构，并且消除了反向电流的放大。 利用这种结构，边缘区域的热负荷降低，因为GTO在预定电压下容忍较高的工作温度。

    CONNECTION ARRANGEMENT FOR SEMICONDUCTOR POWER MODULES
    10.
    发明申请
    CONNECTION ARRANGEMENT FOR SEMICONDUCTOR POWER MODULES 有权
    半导体功率模块的连接布置

    公开(公告)号：US20110233608A1

    公开(公告)日：2011-09-29

    申请号：US13096155

    申请日：2011-04-28

    申请人： Didier COTTET ,  Gunnar Asplund ,  Stefan Linder

    发明人： Didier COTTET ,  Gunnar Asplund ,  Stefan Linder

    IPC分类号： H01L29/739 ,  H01L21/00

    CPC分类号： H01L25/072 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

    摘要翻译： 半导体功率模块包括至少两个子模块。 子模块包括至少一个具有集电极，发射极和栅极的相应晶体管。 所述模块包括具有用于将所述至少两个子模块的集电极连接到外部电路部件的集电极端子单元的连接装置，至少两个用于将所述至少两个子模块的各个发射极分别连接到外部电路的发射极端子单元 以及用于将至少两个子模块的各个门单独地连接到外部电路部件的至少两个栅极端子单元。