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    CONNECTION ARRANGEMENT FOR SEMICONDUCTOR POWER MODULES
    2.
    发明申请
    CONNECTION ARRANGEMENT FOR SEMICONDUCTOR POWER MODULES 有权
    半导体功率模块的连接布置

    公开(公告)号：US20110233608A1

    公开(公告)日：2011-09-29

    申请号：US13096155

    申请日：2011-04-28

    申请人： Didier COTTET ,  Gunnar Asplund ,  Stefan Linder

    发明人： Didier COTTET ,  Gunnar Asplund ,  Stefan Linder

    IPC分类号： H01L29/739 ,  H01L21/00

    CPC分类号： H01L25/072 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

    摘要翻译： 半导体功率模块包括至少两个子模块。 子模块包括至少一个具有集电极，发射极和栅极的相应晶体管。 所述模块包括具有用于将所述至少两个子模块的集电极连接到外部电路部件的集电极端子单元的连接装置，至少两个用于将所述至少两个子模块的各个发射极分别连接到外部电路的发射极端子单元 以及用于将至少两个子模块的各个门单独地连接到外部电路部件的至少两个栅极端子单元。

    IGBT cathode design with improved safe operating area capability
    3.
    发明授权
    IGBT cathode design with improved safe operating area capability 有权
    IGBT阴极设计，具有改进的安全操作面积能力

    公开(公告)号：US07446376B2

    公开(公告)日：2008-11-04

    申请号：US10579837

    申请日：2004-11-16

    申请人： Munaf Rahimo ,  Stefan Linder

    发明人： Munaf Rahimo ,  Stefan Linder

    IPC分类号： H01L29/66

    CPC分类号： B67D1/1422 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

    摘要： In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

    摘要翻译： 在绝缘栅双极晶体管中，根据本发明，通过包括设置在沟道区域（7）中的第一基极区域（81）的双折叠基极区域实现改进的安全工作面积能力，使得其包围 一个或多个源极区域（6），但不与栅极氧化物层（41）下面的第二主表面相邻，并且第二基极区域（82）设置在基极接触区域（821）下面的半导体衬底 ），使得其与沟道区域（7）和第一基极区域（81）部分重叠。

    Method for fabricating semiconductor component with an optimized thickness
    4.
    发明授权
    Method for fabricating semiconductor component with an optimized thickness 有权
    制造具有优化厚度的半导体部件的方法

    公开(公告)号：US06825110B2

    公开(公告)日：2004-11-30

    申请号：US10312729

    申请日：2002-12-30

    申请人： Stefan Linder ,  Hans Rudolf Zeller

    发明人： Stefan Linder ,  Hans Rudolf Zeller

    IPC分类号： H01L214763

    CPC分类号： H01L29/66325 ,  H01L29/36 ,  H01L29/7395

    摘要： In a method for fabricating a semiconductor component with a cathode and an anode from a wafer, the wafer is first provided with a stop zone, thereupon treated on the cathode side and only then reduced in its thickness, so that all that remains of the stop zone is a tail barrier zone. In this case, the stop zone is doped and reduced to the tail barrier zone in such a way that a quantitative optimization of the fabrication method and thus of a thinned semiconductor element is made possible. In said quantitative optimization, diverse parameters and their relation to one another are taken into account, in particular a dopant area density of a tail barrier zone, a dopant density at an anodal surface of the tail harrier zone, a dopant density of a base, a characteristic decay length or slope of the doping profile of the tail barrier zone, and also a thickness of a base—resulting from the wafer—from anode to cathode.

    摘要翻译： 在从晶片制造具有阴极和阳极的半导体部件的方法中，晶片首先设置有停止区域，然后在阴极侧进行处理，然后仅在其厚度上减小，使得所有剩下的停止 区域是尾部阻挡区域。 在这种情况下，停止区被掺杂并还原成尾部阻挡区，使得制造方法和减薄的半导体元件的定量优化成为可能。 在所述定量优化中，考虑了各种参数及其彼此之间的关系，特别是尾部阻挡区的掺杂剂区域密度，尾部区域的阳极表面处的掺杂剂密度，基底的掺杂剂密度， 尾阻挡区域的掺杂分布的特征衰减长度或斜率，以及从晶片从阳极到阴极的基底厚度。

    Method of manufacturing a semiconductor device having a cathode and an anode from a wafer
    5.
    发明授权
    Method of manufacturing a semiconductor device having a cathode and an anode from a wafer 有权
    从晶片制造具有阴极和阳极的半导体器件的方法

    公开(公告)号：US06762080B2

    公开(公告)日：2004-07-13

    申请号：US10224495

    申请日：2002-08-21

    申请人： Stefan Linder

    发明人： Stefan Linder

    IPC分类号： H01L21332

    CPC分类号： H01L29/66333 ,  H01L29/66363

    摘要： In a method of manufacturing a semiconductor element (6) having a cathode (3) and an anode (5), the starting material used is a relatively thick wafer (1) to which, as a first step, a barrier region (21) is added on the anode side. It is then treated on the cathode side, and the thickness of the wafer (1) is then reduced on the side opposite to the cathode (3), and an anode (5) is produced on this side in a further step. The result is a relatively thin semiconductor element which can be produced economically and without epitaxial layers.

    摘要翻译： 在制造具有阴极（3）和阳极（5）的半导体元件（6）的方法中，所使用的起始材料是相对较厚的晶片（1），作为第一步骤，作为第一步骤的阻挡区域（21） 添加在阳极侧。 然后在阴极侧进行处理，然后在与阴极（3）相反的一侧减小晶片（1）的厚度，并在该侧再制造阳极（5）。 结果是可以经济地生产并且没有外延层的相对薄的半导体元件。

    Radio frequency identification transponder having integrated antenna
    6.
    发明授权
    Radio frequency identification transponder having integrated antenna 失效
    具有集成天线的射频识别应答器

    公开(公告)号：US06268796B1

    公开(公告)日：2001-07-31

    申请号：US08989255

    申请日：1997-12-12

    申请人： Alfred Gnadinger ,  Stefan Linder

    发明人： Alfred Gnadinger ,  Stefan Linder

    IPC分类号： G08B1314

    CPC分类号： G08B13/2414 ,  G06K19/0726 ,  G06K19/07749 ,  G06K19/07758 ,  G06K19/07775 ,  G06K19/07779 ,  G06K19/07781 ,  G08B13/2417 ,  G08B13/2431 ,  G08B13/2437 ,  H01Q7/06

    摘要： A radio frequency identification device (RFID) has an antenna formed on a chip. The chip has backside and a front side coated with conductive traces, which are connected through conductive traces on the sides of two elongate through-hole slots formed on the chip to form an operative coil having the chip as a core. In one embodiment, the antenna chip may be stacked above an integrated circuit. In another embodiment, the integrated circuit may be formed on the antenna chip. The antenna chip may include a high magnetic permeability layer to increase the inductance of the coil, a capacitor to tune the coil to a desired frequency, and a coupling capacitor to power the integrated circuit. As well as the specific application disclosed, an inductance useful in numerous applications can be formed according to the above structure.

    摘要翻译： 射频识别装置（RFID）具有形成在芯片上的天线。 芯片具有背面，并且前面涂有导电迹线，导电迹线通过形成在芯片上的两个细长通孔槽的侧面上的导电迹线连接，形成具有芯片为芯的操作线圈。 在一个实施例中，天线芯片可以堆叠在集成电路之上。 在另一个实施例中，集成电路可以形成在天线芯片上。 天线芯片可以包括高磁导率层，以增加线圈的电感，用于将线圈调谐到期望频率的电容器，以及用于为集成电路供电的耦合电容器。 除了所公开的具体应用之外，可以根据上述结构形成在许多应用中有用的电感。

    Connection arrangement for semiconductor power modules
    7.
    发明授权
    Connection arrangement for semiconductor power modules 有权
    半导体电源模块的连接布置

    公开(公告)号：US09024421B2

    公开(公告)日：2015-05-05

    申请号：US13096155

    申请日：2011-04-28

    申请人： Didier Cottet ,  Gunnar Asplund ,  Stefan Linder

    发明人： Didier Cottet ,  Gunnar Asplund ,  Stefan Linder

    IPC分类号： H01L23/02 ,  H01L25/07

    CPC分类号： H01L25/072 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

    摘要翻译： 半导体功率模块包括至少两个子模块。 子模块包括至少一个具有集电极，发射极和栅极的相应晶体管。 所述模块包括具有用于将所述至少两个子模块的集电极连接到外部电路部件的集电极端子单元的连接装置，至少两个用于将所述至少两个子模块的各个发射极分别连接到外部电路的发射极端子单元 以及用于将至少两个子模块的各个门单独地连接到外部电路部件的至少两个栅极端子单元。

    Power semiconductor
    8.
    发明授权
    Power semiconductor 有权
    功率半导体

    公开(公告)号：US08501586B2

    公开(公告)日：2013-08-06

    申请号：US11812030

    申请日：2007-06-14

    申请人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    发明人： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

    摘要： In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

    摘要翻译： 为了产生用于在高阻挡电压下操作的功率半导体，在具有掺杂第一电荷载体类型的相同电荷载流子型的中等掺杂层的轻掺杂层上产生。 在远离轻掺杂层的介质掺杂层的该侧产生高掺杂层，其中高掺杂层保留在最终半导体中的具有高掺杂的部分形成第二阻挡层，其中掺杂 高掺杂层比掺杂中掺杂层高。 随后将电极扩散到高掺杂层中。 保留在成品半导体中的低掺杂部分形成漂移层，剩余的中等掺杂部分形成第一停止层。

    Power semiconductor module
    10.
    发明授权
    Power semiconductor module 有权
    功率半导体模块

    公开(公告)号：US06738258B2

    公开(公告)日：2004-05-18

    申请号：US10302824

    申请日：2002-11-25

    申请人： Bo Bijlenga ,  Fabian Zwick ,  Stefan Linder ,  Patrick Erne

    发明人： Bo Bijlenga ,  Fabian Zwick ,  Stefan Linder ,  Patrick Erne

    IPC分类号： H05K720

    CPC分类号： H01L24/72 ,  H01L25/115 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/00

    摘要： The power semiconductor module (1) comprises a housing (5), a covering panel (11) and at least two submodules (21, 22). The submodules (21, 22) each comprise at least one semiconductor chip, which has two main electrodes which are electrically conductively connected to main connections (3, 4) of the submodules. The submodules (21, 22) are arranged alongside one another, and one of their two main surfaces is pressed against the covering panel (11) of the module. The submodules are electrically connected in series. The maximun blocking voltage of the module is doubled by connecting the submodules, which are arranged alongside one another, in series. This reduces the length and the costs of the stack for hihg-voltage switch since fewer components are required for the same blocking voltages, in particular fewer modules and cooling elements.

    摘要翻译： 功率半导体模块（1）包括壳体（5），覆盖板（11）和至少两个子模块（21,22）。 子模块（21,22）各自包括至少一个半导体芯片，其具有导电连接到子模块的主连接（3,4）的两个主电极。 子模块（21,22）彼此并排布置，并且其两个主表面中的一个压靠在模块的覆盖板（11）上。 子模块串联电连接。 通过连接彼此并排布置的子模块将模块的最大阻断电压加倍。 这减少了用于高压开关的堆叠的长度和成本，因为对于相同的阻挡电压，特别是较少的模块和冷却元件需要更少的部件。