公开(公告)号：US20170249254A9

公开(公告)日：2017-08-31

申请号：US14055367

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20170235491A1

公开(公告)日：2017-08-17

申请号：US15583920

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK ,  John MASHEY ,  Mark HAIRGROVE ,  Chenghuan JIA ,  Cameron BUSCHARDT ,  Lucien DUNNING ,  Brian FAHS

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F12/1009

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0664 ,  G06F12/0804 ,  G06F12/1009 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/657

Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

公开(公告)号：US20170185526A9

公开(公告)日：2017-06-29

申请号：US14055382

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20140281324A1

公开(公告)日：2014-09-18

申请号：US14134142

申请日：2013-12-19

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY ,  James M. VAN DYKE

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

Abstract translation: 本发明的一个实施例提出了一种用于将存储器页从第一存储器迁移到第二存储器的计算机实现的方法。 该方法包括确定由第一存储器支持的第一页大小。 该方法还包括确定由第二存储器支持的第二页大小。 该方法还包括基于与存储器页相关联的页面状态目录中的条目来确定存储器页面的使用历史。 该方法还包括基于第一页面大小，第二页面大小和使用历史来在第一存储器和第二存储器之间迁移存储器页面。

公开(公告)号：US20140281299A1

公开(公告)日：2014-09-18

申请号：US14133489

申请日：2013-12-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F12/08 ,  G06F12/1009 ,  G06F2212/251 ,  G06F2212/301

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

Abstract translation: 公开了用于在虚拟存储器子系统中的存储器之间转换存储器页面的技术。 统一虚拟存储器（UVM）驱动程序响应于与第一存储器页相关联的存储器访问请求来检测页面错误，其中本地页表不包括与包括在存储器访问请求中的虚拟存储器地址相对应的条目。 UVM驱动程序响应页面错误，执行页面故障序列。 页面错误序列包括将与第一存储器页相关联的所有权状态修改为中央处理单元共享。 页面错误序列还包括调度第一存储器页面以从与中央处理单元（CPU）相关联的系统存储器迁移到与并行处理单元（PPU）相关联的本地存储器。 所公开的方法的一个优点是PPU以更高的效率访问存储器页面。

公开(公告)号：US20140267334A1

公开(公告)日：2014-09-18

申请号：US14011671

申请日：2013-08-27

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06T1/60

CPC classification number: G06F11/073 ,  G06F11/0751 ,  G06T1/20 ,  G06T1/60

Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.

Abstract translation: 本发明的一个实施例包括第一处理单元在与第二处理单元共享的存储页上执行原子操作的技术。 存储器页面与对应于第一处理单元的页表项相关联。 在执行原子操作之前，包括在第一处理单元中的MMU评估包含在页表项中的原子许可位。 如果MMU确定原子许可位不活动，则两个处理单元协调更改存储器页面的许可状态。 作为状态更改的一部分，页表项中的原子许可位被激活。 随后，第一处理单元执行由第二处理单元不中断的原子操作。 有利地，通过原子许可位来协调处理单元确保原子操作的适当且有效的执行。