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    TECHNIQUES FOR ASSIGNING PRIORITIES TO MEMORY COPIES
    3.
    发明申请
    TECHNIQUES FOR ASSIGNING PRIORITIES TO MEMORY COPIES 有权
    记忆复制优先的技术

    公开(公告)号：US20140344528A1

    公开(公告)日：2014-11-20

    申请号：US13897193

    申请日：2013-05-17

    Applicant: Nvidia Corporation

    Inventor： Vivek KINI ,  Christopher LAMB ,  Mark HAIRGROVE

    IPC: G06F13/16

    CPC classification number: G06F13/1663 ,  G06F9/52 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/18

    Abstract: One embodiment sets forth a method for guiding the order in which a parallel processing subsystem executes memory copies. A driver creates semaphores for all but the lowest priority included in a plurality of priorities and associates one priority with each copy hardware channel included in the parallel processing subsystem. The driver then aliases prioritized streams to the copy hardware channels based on the priorities. Upon receiving a request to execute a memory copy within one of the streams, the driver inserts commands into the aliased copy hardware channel. These commands use the semaphores to direct the parallel processing subsystem to execute the memory copy based on the priority of the copy hardware channel. Advantageously, by assigning priorities to streams and, subsequently, strategically requesting memory copies within the prioritized streams, an application developer may fine-tune their software application to increase the overall processing efficiency of the software application.

    Abstract translation: 一个实施例提出了一种用于指导并行处理子系统执行存储器拷贝的顺序的方法。 驱动程序为包含在多个优先级中的除了最低优先级之外的所有者创建信号量，并且将包括在并行处理子系统中的每个复制硬件信道的优先级与一个优先级相关联。 然后，驱动程序根据优先级将优先级流复制到复制硬件通道。 在接收到在其中一个流中执行存储器副本的请求时，驱动程序将命令插入到别名复制硬件通道中。 这些命令使用信号指示并行处理子系统根据复制硬件通道的优先级执行存储器复制。 有利地，通过为流分配优先级，并且随后在优先级流中策略地请求存储器副本，应用开发者可以微调其软件应用以提高软件应用的整体处理效率。

    MIGRATION OF PEER-MAPPED MEMORY PAGES
    4.
    发明申请
    MIGRATION OF PEER-MAPPED MEMORY PAGES 有权
    对等记录页的移植

    公开(公告)号：US20140281297A1

    公开(公告)日：2014-09-18

    申请号：US14134148

    申请日：2013-12-19

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  Chenghuan JIA ,  Cameron BUSCHARDT ,  Lucien DUNNING ,  Brian FAHS

    IPC: G06F12/10 ,  G06F12/12

    CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0664 ,  G06F12/0804 ,  G06F12/1009 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/657

    Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

    Abstract translation: 提供了技术，通过该技术可以在多PPU系统中的PPU存储器之间迁移存储器页面。 根据这些技术，UVM驱动程序确定特定存储器页面应该改变所有权状态和/或在一个PPU存储器和另一个PPU存储器之间迁移。 响应于该确定，UVM驱动程序启动对等体转换序列以使存储器页的所有权状态和/或位置改变。 各种对等体转换序列涉及修改一个或多个PPU的映射，以及将存储器页面从一个PPU存储器复制到另一个PPU存储器。 可以并行执行对等转换序列中的几个步骤，以提高处理速度。

    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
    6.
    发明申请
    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20140281364A1

    公开(公告)日：2014-09-18

    申请号：US14011643

    申请日：2013-08-27

    Applicant: NVIDIA CORPORATION

    Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F2212/301

    Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

    FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM
    7.
    发明申请
    FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
    用于跟踪统一的虚拟内存系统中的页面故障的故障缓冲区

    公开(公告)号：US20140281296A1

    公开(公告)日：2014-09-18

    申请号：US14055345

    申请日：2013-10-16

    Applicant: NVIDIA Corporation

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

    IPC: G06F11/07 ,  G06F12/12

    CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

    Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，产生第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

    PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY
    8.
    发明申请
    PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY 有权
    用于管理统一的虚拟内存的页面状态目录

    公开(公告)号：US20140281255A1

    公开(公告)日：2014-09-18

    申请号：US14055318

    申请日：2013-10-16

    Applicant: NVIDIA Corporation

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

    Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，生成第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM
    10.
    发明申请
    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190340145A1

    公开(公告)日：2019-11-07

    申请号：US16450830

    申请日：2019-06-24

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

    IPC: G06F13/40 ,  G06F12/123

    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

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