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公开(公告)号:US12020035B2
公开(公告)日:2024-06-25
申请号:US17691288
申请日:2022-03-10
Applicant: NVIDIA Corporation
Inventor: Apoorv Parle , Ronny Krashinsky , John Edmondson , Jack Choquette , Shirish Gadre , Steve Heinrich , Manan Patel , Prakash Bangalore Prabhakar, Jr. , Ravi Manyam , Wish Gandhi , Lacky Shah , Alexander L. Minkin
IPC: G06F5/06 , G06F9/38 , G06F9/48 , G06F9/52 , G06F13/16 , G06F13/40 , G06T1/20 , G06T1/60 , H04L49/101
CPC classification number: G06F9/3887 , G06F9/522 , G06F13/1689 , G06F13/4022 , G06T1/20 , G06T1/60 , H04L49/101
Abstract: This specification describes a programmatic multicast technique enabling one thread (for example, in a cooperative group array (CGA) on a GPU) to request data on behalf of one or more other threads (for example, executing on respective processor cores of the GPU). The multicast is supported by tracking circuitry that interfaces between multicast requests received from processor cores and the available memory. The multicast is designed to reduce cache (for example, layer 2 cache) bandwidth utilization enabling strong scaling and smaller tile sizes.
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公开(公告)号:US20240169471A1
公开(公告)日:2024-05-23
申请号:US18086476
申请日:2022-12-21
Applicant: NVIDIA Corporation
Inventor: Harold Carter Edwards , Stephen Anthony Bernard Jones , Alexander Lev Minkin , Olivier Giroux , Gokul Ramaswamy Hirisave Chandra Shekhara , Aditya Avinash Atluri , Apoorv Parle , Ronny Meir Krashinsky , Alan Kaatz , Andrew Robert Kerr , Jack H. Choquette
IPC: G06T1/60 , G06F12/0811 , G06F12/0862 , G06T1/20
CPC classification number: G06T1/60 , G06F12/0811 , G06F12/0862 , G06T1/20 , G06F2212/62
Abstract: Apparatuses, systems, and techniques to perform a graphics processing unit (GPU) prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches. In at least one embodiment, one or more circuits of a GPU are to perform a GPU prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches.
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23.
公开(公告)号:US20240168795A1
公开(公告)日:2024-05-23
申请号:US18081552
申请日:2022-12-14
Applicant: NVIDIA Corporation
Inventor: Harold Carter Edwards , Olivier Giroux , Jack H. Choquette , Gokul Ramaswamy Hirisave Chandra Shekhara , Rui Guo , Chao Li , Vishalkumar Ketankumar Mehta , David Dastous St. Hilaire , Aditya Avinash Atluri , Apoorv Parle , Ronny Meir Krashinsky , Subhasmita Chakraborty , Vikram Dhar
CPC classification number: G06F9/467 , G06F9/3004 , G06F9/3877 , G06F9/541
Abstract: Apparatuses, systems, and techniques to perform delayed memory transaction information check. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided by one or more users about one or more memory transactions after a timeout event indicated by one or more users.
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24.
公开(公告)号:US20240168763A1
公开(公告)日:2024-05-23
申请号:US18072300
申请日:2022-11-30
Applicant: NVIDIA Corporation
Inventor: Harold Carter Edwards , Kyrylo Perelygin , Maciej Tyrlik , Gokul Ramaswamy Hirisave Chandra Shekhara , Balaji Krishna Yugandhar Atukuri , Rishkul Kulkarni , Konstantinos Kyriakopoulos , Edward H. Gornish , David Allan Berson , Bageshri Sathe , James Player , Aman Arora , Alan Kaatz , Andrew Kerr , Haicheng Wu , Cris Cecka , Vijay Thakkar , Sean Treichler , Jack H. Choquette , Aditya Avinash Atluri , Apoorv Parle , Ronny Meir Krashinsky , Cody Addison , Girish Bhaskarrao Bharambe
CPC classification number: G06F9/3001 , G06F17/16
Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause two or more other computational operations to be performed by two or more streaming multiprocessors (SMs).
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公开(公告)号:US20240168762A1
公开(公告)日:2024-05-23
申请号:US18072081
申请日:2022-11-30
Applicant: NVIDIA Corporation
Inventor: Harold Carter Edwards , Kyrylo Perelygin , Maciej Tyrlik , Gokul Ramaswamy Hirisave Chandra Shekhara , Balaji Krishna Yugandhar Atukuri , Rishkul Kulkarni , Konstantinos Kyriakopoulos , Edward H. Gornish , David Allan Berson , Bageshri Sathe , James Player , Aman Arora , Alan Kaatz , Andrew Kerr , Haicheng Wu , Cris Cecka , Vijay Thakkar , Sean Treichler , Jack H. Choquette , Aditya Avinash Atluri , Apoorv Parle , Ronny Meir Krashinsky , Cody Addison , Girish Bhaskarrao Bharambe
CPC classification number: G06F9/3001 , G06F9/3009 , G06F17/16
Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.
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26.
公开(公告)号:US20240168659A1
公开(公告)日:2024-05-23
申请号:US18086429
申请日:2022-12-21
Applicant: NVIDIA Corporation
Inventor: Harold Carter Edwards , Stephen Anthony Bernard Jones , Alexander Lev Minkin , Olivier Giroux , Gokul Ramaswamy Hirisave Chandra Shekhara , Aditya Avinash Atluri , Apoorv Parle , Chao Li , Ronny Meir Krashinsky , Alan Kaatz , Andrew Robert Kerr , Jack H. Choquette
IPC: G06F3/06 , G06F12/0862
CPC classification number: G06F3/0625 , G06F3/0646 , G06F3/0659 , G06F3/0673 , G06F12/0862 , G06F2212/608
Abstract: Apparatuses, systems, and techniques to transform and store information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed and stored.
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