公开(公告)号：US20160104671A1

公开(公告)日：2016-04-14

申请号：US14970160

申请日：2015-12-15

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L29/06 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

公开(公告)号：US20110183512A1

公开(公告)日：2011-07-28

申请号：US12793843

申请日：2010-06-04

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jong-Cheol Lee

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jong-Cheol Lee

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.

摘要翻译： 形成半导体器件的方法包括在衬底上形成下导电图案，在下导电图案上形成绝缘层，形成通过绝缘层的接触孔，露出下导电图案，沿着第 接触孔，然后在接触孔中形成接触塞。 接触塞形成为接触下导电图案。

公开(公告)号：US09231104B2

公开(公告)日：2016-01-05

申请号：US14527450

申请日：2014-10-29

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L27/105 ,  H01L29/45 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US20150048444A1

公开(公告)日：2015-02-19

申请号：US14527450

申请日：2014-10-29

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L27/105

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US08486787B2

公开(公告)日：2013-07-16

申请号：US13075334

申请日：2011-03-30

申请人： Nam-Gun Kim ,  Sung-Il Cho ,  Yoon-Jae Kim ,  Doo-Young Lee

发明人： Nam-Gun Kim ,  Sung-Il Cho ,  Yoon-Jae Kim ,  Doo-Young Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894

摘要： A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.

摘要翻译： 制造半导体器件的方法包括形成具有比第二接触开口更大的深度的第一接触开口，以通过绝缘层暴露第一和第二接触，其中第一和第二接触件相对于上部 绝缘层表面。 因此，可以防止第二接触开口的过度的过度蚀刻，并使对由第二接触开口露出的接触区域的蚀刻损伤最小化。

公开(公告)号：US20130056823A1

公开(公告)日：2013-03-07

申请号：US13603045

申请日：2012-09-04

申请人： Yoonjae Kim ,  Nam-Gun Kim ,  Chulho Shin ,  Chan Min Lee

发明人： Yoonjae Kim ,  Nam-Gun Kim ,  Chulho Shin ,  Chan Min Lee

IPC分类号： H01L29/78

CPC分类号： H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures.

摘要翻译： 在衬底中形成器件隔离层，以在衬底中限定间隔开的线性有源区。 掩埋栅极图案形成在衬底中并且沿着第一方向延伸以跨过有源区域。 在基板上形成蚀刻停止层和第一绝缘层。 位线结构形成在第一绝缘层上并且沿着横向于第一方向的第二方向延伸以穿过有源区。 在位线结构上形成第二绝缘层。 穿过第二绝缘层，第一绝缘层和蚀刻停止层的接触插塞接触相邻的位线结构中的一个有源区。

公开(公告)号：US20110256719A1

公开(公告)日：2011-10-20

申请号：US13075334

申请日：2011-03-30

申请人： Nam-Gun Kim ,  Sung-Il Cho ,  Yoon-Jae Kim ,  Doo-Young Lee

发明人： Nam-Gun Kim ,  Sung-Il Cho ,  Yoon-Jae Kim ,  Doo-Young Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894

摘要： A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.

摘要翻译： 制造半导体器件的方法包括形成具有比第二接触开口更大的深度的第一接触开口，以通过绝缘层暴露第一和第二接触，其中第一和第二接触件相对于上部 绝缘层表面。 因此，可以防止第二接触开口的过度的过度蚀刻，并使对由第二接触开口露出的接触区域的蚀刻损伤最小化。

公开(公告)号：US20160197042A1

公开(公告)日：2016-07-07

申请号：US15071452

申请日：2016-03-16

申请人： EUN-OK LEE ,  Nam-Gun Kim ,  Gyuhwan Oh ,  Heesook Park ,  Hyun-Jung Lee ,  Kyungho Jang

发明人： EUN-OK LEE ,  Nam-Gun Kim ,  Gyuhwan Oh ,  Heesook Park ,  Hyun-Jung Lee ,  Kyungho Jang

IPC分类号： H01L23/532

CPC分类号： H01L23/5329 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

摘要翻译： 覆盖接触塞的侧壁的间隔件包括相对更受损的第一部分和相对较少受损的第二部分。 间隔物的第一和第二部分的界面与接触塞的金属硅化物层间隔开。 因此，可以提高半导体器件的可靠性。 还描述了相关的制造方法。

公开(公告)号：US09214382B2

公开(公告)日：2015-12-15

申请号：US14290620

申请日：2014-05-29

申请人： Eun-Ok Lee ,  Nam-Gun Kim ,  Gyuhwan Oh ,  Heesook Park ,  Hyun-Jung Lee ,  Kyungho Jang

发明人： Eun-Ok Lee ,  Nam-Gun Kim ,  Gyuhwan Oh ,  Heesook Park ,  Hyun-Jung Lee ,  Kyungho Jang

IPC分类号： H01L21/764 ,  H01L27/108

CPC分类号： H01L23/5329 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

摘要翻译： 覆盖接触塞的侧壁的间隔件包括相对更受损的第一部分和相对较少受损的第二部分。 间隔物的第一和第二部分的界面与接触塞的金属硅化物层间隔开。 因此，可以提高半导体器件的可靠性。 还描述了相关的制造方法。

公开(公告)号：US08461687B2

公开(公告)日：2013-06-11

申请号：US13072907

申请日：2011-03-28

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/40 ,  H01L29/66

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。