公开(公告)号：US08006076B2

公开(公告)日：2011-08-23

申请号：US12110491

申请日：2008-04-28

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/48 ,  G06F9/52

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

公开(公告)号：US07984243B2

公开(公告)日：2011-07-19

申请号：US10577133

申请日：2004-11-02

申请人： Hazuki Kawai ,  Ryuta Nakanishi ,  Tetsuya Tanaka ,  Shuji Miyasaka

发明人： Hazuki Kawai ,  Ryuta Nakanishi ,  Tetsuya Tanaka ,  Shuji Miyasaka

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/121

摘要： A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.

摘要翻译： 根据本发明的高速缓冲存储器包括：W标志设置单元，其修改指示保存高速缓存的数据单元的每个高速缓存条目的访问顺序的顺序数据，以反映实际的访问顺序;以及替换单元，其选择高速缓存条目 根据修改的订单数据进行替换，并替换高速缓存条目。

公开(公告)号：US07953935B2

公开(公告)日：2011-05-31

申请号：US11816858

申请日：2006-02-08

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

IPC分类号： G06F13/00

CPC分类号： G06F12/12 ,  G06F12/0802 ,  G06F12/0893

摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。

公开(公告)号：US20090049219A1

公开(公告)日：2009-02-19

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 为了提供能够执行异常处理程序与正常处理之间的切换的信息处理装置，所述信息处理装置包括：信息处理装置，包括：处理器; 数据处理单元，用于在从所述处理器接收到处理请求时执行特定处理; 中断控制器，用于向所述处理器发出中断请求; 以及异常控制单元，其可操作以控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接，所述数据处理单元包括通知单元，用于经由所述专用线通知所述异常控制单元 表示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以执行异常处理程序 处理器。

公开(公告)号：US20080209407A1

公开(公告)日：2008-08-28

申请号：US12109707

申请日：2008-04-25

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F9/45

CPC分类号： G06F9/30072 ,  G06F8/447 ,  G06F9/325

摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指​​令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。

公开(公告)号：US20080046687A1

公开(公告)日：2008-02-21

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F15/80

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US07076638B2

公开(公告)日：2006-07-11

申请号：US10246482

申请日：2002-09-19

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US20060031661A1

公开(公告)日：2006-02-09

申请号：US11245357

申请日：2005-10-07

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/40

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US20060024607A1

公开(公告)日：2006-02-02

申请号：US11190934

申请日：2005-07-28

申请人： Tetsuya Tanaka ,  Nobuyasu Makino ,  Hideyuki Santo

发明人： Tetsuya Tanaka ,  Nobuyasu Makino ,  Hideyuki Santo

IPC分类号： G03G5/00

CPC分类号： B02C19/066 ,  B02C19/065 ,  B02C23/10 ,  G03G9/0817

摘要： A pulverization/classification apparatus includes a plurality of air nozzles, a milling chamber as a space for pulverizing particles by compressed air jetted by the air nozzles, and a rotor installed at an upper part of the milling chamber that classifies powder materials flowing into the rotor from the milling chamber with centrifuging into fine particles and coarse particles. The rotor includes plural blade members, and a width of the blade members within the rotor are set to be 1/50- 2/25 of the rotor's diameter.

摘要翻译： 粉碎/分级装置包括多个空气喷嘴，作为用于通过空气喷嘴喷射的压缩空气粉碎颗粒的研磨室和安装在研磨室的上部的转子，其分级流入转子的粉末材料 从研磨室离心分离成细颗粒和粗颗粒。 转子包括多个叶片构件，并且转子内的叶片构件的宽度被设定为转子直径的1 / 50-2 / 25。

公开(公告)号：US20050252395A1

公开(公告)日：2005-11-17

申请号：US11129510

申请日：2005-05-13

申请人： Takaaki Sakaue ,  Yuji Otake ,  Masafumi Nishida ,  Tetsuya Tanaka

发明人： Takaaki Sakaue ,  Yuji Otake ,  Masafumi Nishida ,  Tetsuya Tanaka

IPC分类号： B41F15/26 ,  B41F15/08 ,  B41F15/36 ,  B41F15/40 ,  H05K3/12 ,  H05K3/34 ,  G03F1/00 ,  B41L13/18

CPC分类号： H05K3/1216 ,  B41P2215/14 ,  H05K2201/10393 ,  H05K2203/0165

摘要： In a screen printing apparatus for contacting a lower surface of a mask plate with a substrate and moving a squeezee in a sliding motion on an upper surface of the mask plate thereby printing a paste onto the substrate, mask bend preventing members are mounted on conveying rails at front and rear parts of clamp members clamping the substrate in a Y-direction, and, at a mask separating operation after printing, the substrate is lowered while the lower surface of the mask plate is supported by the clamp members and the mask bend preventing members. Thus the mask separation can be achieved in a state where the mask plate is supported from below on four sides of the substrate and is thus prevented from a downward bending, and a satisfactory mask separating property can be ensured over the entire substrate.

摘要翻译： 在丝网印刷装置中，将掩模板的下表面与基板接触并且在所述掩模板的上表面上以滑动方式移动挤压机，从而将糊状物印刷到所述基板上，将掩模弯曲防止部件安装在输送轨道 在夹持基板的Y方向的夹持部件的前部和后部，在印刷后的掩模分离操作中，基板被降低，而掩模板的下表面被夹持部件支撑，并且防止掩模弯曲 会员 因此，掩模分离可以在掩模板从基板的四侧的下方支撑的状态下实现，从而防止向下弯曲，并且可以在整个基板上确保令人满意的掩模分离性能。