公开(公告)号：US07930520B2

公开(公告)日：2011-04-19

申请号：US12110539

申请日：2008-04-28

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F1/32

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

公开(公告)号：US20100180095A1

公开(公告)日：2010-07-15

申请号：US12095610

申请日：2006-11-28

申请人： Masanori Fujibayashi ,  Nobuo Higaki ,  Kazushi Kurata ,  Tomoko Matsui

发明人： Masanori Fujibayashi ,  Nobuo Higaki ,  Kazushi Kurata ,  Tomoko Matsui

IPC分类号： G06F12/14

CPC分类号： G06F5/14 ,  G06F2205/062

摘要： The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer.

摘要翻译： 本发明的缓冲器控制装置包括：保持与读指针不同的虚拟指针和写指针的指针保持单元; 访问控制单元，其控制对环形缓冲器的访问; 判断单元，判断读指针和写指针之一是否达到与虚拟指针所指示的地址基本相同的地址; 以及禁止单元，其在所述读取指针和所述写入指针之一达到与所述虚拟指针所指示的地址基本相同的地址的情况下，使用所述读取指针和所述写入指针中的一者禁止正常访问 正常访问由访问控制单元控制，其中访问控制单元进一步控制对环形缓冲器的重新访问。

公开(公告)号：US20100169614A1

公开(公告)日：2010-07-01

申请号：US12705300

申请日：2010-02-12

申请人： Shuichi TAKAYAMA ,  Nobuo Higaki

发明人： Shuichi TAKAYAMA ,  Nobuo Higaki

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/3853

摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1） 指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

公开(公告)号：US20090063734A1

公开(公告)日：2009-03-05

申请号：US11817094

申请日：2006-02-27

申请人： Kazushi Kurata ,  Nobuo Higaki

发明人： Kazushi Kurata ,  Nobuo Higaki

IPC分类号： G06F3/00

CPC分类号： G06F13/28 ,  G06F13/4059

摘要： A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush.

摘要翻译： 一种总线控制器，能够在完成冲洗之前缩短所需的时间，从而不降低处理器的性能。 总线控制器包括：FIFO，用于将先前从处理器存储的数据暂时保存在存储器中; 用于保持指示器的刷新指针，其指示在接收到触发信号时由FIFO保持的结束数据; 存储器控制单元，用于根据触发信号将由FIFO保存的数据的一部分写入存储器，以部分地刷新FIFO，该部分从开始数据到由刷新指针指示的结束数据; 以及等待电路，用于产生由处理器执行的特定访问指令的等待信号，直到存储器控制单元完成部分刷新。

公开(公告)号：US20090037779A1

公开(公告)日：2009-02-05

申请号：US11916319

申请日：2006-06-06

申请人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

发明人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

IPC分类号： G06F12/00 ,  G06F11/07

CPC分类号： G06F13/385

摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

摘要翻译： 响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到 并将写入数据写入由写入地址指定的外部设备。 当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

公开(公告)号：US20080209192A1

公开(公告)日：2008-08-28

申请号：US12110513

申请日：2008-04-28

申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/22

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

公开(公告)号：US07362887B2

公开(公告)日：2008-04-22

申请号：US10965919

申请日：2004-10-18

申请人： Takahiro Oohashi ,  Naoaki Sumida ,  Nobuo Higaki

发明人： Takahiro Oohashi ,  Naoaki Sumida ,  Nobuo Higaki

IPC分类号： G06K9/00

CPC分类号： G06K9/00248 ,  G06K9/00234 ,  G06K9/00261

摘要： A face identification apparatus for identifying a face is designed to have a face region expectation measure for expecting his/her face region within the image; a pupil-candidate-point detection measure for converting the face region to an image of a standard size, making it a standard image, and detecting his/her right/left pupil candidate points out of a search region within the standard image; a reference data generation measure for generating a normalization image from the standard image with making it a standard a distance of the right/left pupil candidate points and making reference data for evaluating advisability of the face region from the normalization image; and a face region evaluation measure for obtaining a degree of approximation between the reference data and standard data prepared in advance and evaluating the advisability of the face region.

摘要翻译： 用于识别脸部的面部识别装置被设计为具有用于期望他/她的脸部区域在图像内的面部区域期望度量; 用于将脸部区域转换为标准尺寸的图像的瞳孔候选点检测措施，使其成为标准图像，并且从标准图像内的搜索区域检测他/她的右/左瞳孔候选点; 参考数据生成措施，用于从所述标准图像生成标准化图像，使其成为所述右/左瞳孔候选点的标准距离，并且从所述标准化图像中提取用于评估所述面部区域的可取性的参考数据; 以及面部区域评价措施，用于获得参考数据和预先准备的标准数据之间的近似度，并评估面部区域的可取性。

公开(公告)号：US07080367B2

公开(公告)日：2006-07-18

申请号：US10051335

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：USRE39121E1

公开(公告)日：2006-06-06

申请号：US10366502

申请日：2003-02-13

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D 1”被解码时，积和结果寄存器6将其保持值输出到路径P 1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US06976250B2

公开(公告)日：2005-12-13

申请号：US10045802

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F717/151

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。