Image sensor with voltage buffer for self-test

    公开(公告)号:US11122259B2

    公开(公告)日:2021-09-14

    申请号:US16793345

    申请日:2020-02-18

    Abstract: A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.

    Image Sensor With Voltage Buffer For Self-Test

    公开(公告)号:US20210258563A1

    公开(公告)日:2021-08-19

    申请号:US16793345

    申请日:2020-02-18

    Abstract: A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.

    IMAGE SENSOR FAR END DRIVER CIRCUITRY PROVIDING FAST SETTLING ROW CONTROL SIGNALS

    公开(公告)号:US20210152756A1

    公开(公告)日:2021-05-20

    申请号:US16685663

    申请日:2019-11-15

    Abstract: An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.

    IMAGE SENSOR POWER SUPPLY NOISE DETECTION

    公开(公告)号:US20170168104A1

    公开(公告)日:2017-06-15

    申请号:US14964159

    申请日:2015-12-09

    CPC classification number: G01R29/26 G01R31/40

    Abstract: A power supply noise measurement circuit includes a multiphase filter coupled to receive a power supply signal. The multiphase filter is coupled to output a first filtered power supply signal for a first phase, and a second filtered power supply signal for a second phase. A multiphase amplifier is coupled to the multiphase filter to sample offset voltages in response to the first filter power supply signal during the first phase to set up DC operation points in the multiphase amplifier, and generate an amplified power supply noise signal during the second phase. An overshoot detector is coupled to the multiphase amplifier to detect overshoot events in the amplified power supply noise signal, and an undershoot detector is coupled to the multiphase amplifier to detect undershoot events in the amplified power supply noise signal.

    Image sensor power supply rejection ratio improvement through ramp generator in continuous time readout circuitry
    25.
    发明授权
    Image sensor power supply rejection ratio improvement through ramp generator in continuous time readout circuitry 有权
    通过连续时间读出电路中的斜坡发生器改善图像传感器电源抑制比

    公开(公告)号:US09571775B1

    公开(公告)日:2017-02-14

    申请号:US14942622

    申请日:2015-11-16

    CPC classification number: H04N5/378 H04N5/3698

    Abstract: A ramp generator for use in readout circuitry includes an integrator coupled to receive a ramp generator input reference signal to generate a reference ramp signal coupled to be received by an analog to digital converter. A power supply compensation circuit that is coupled to generate the ramp generator input reference signal includes a delay circuit including a variable resistor and a filter capacitor coupled to receive a power supply signal. The variable resistor is tuned to match a delay ripple from the power supply to a bitline output. A capacitive voltage divider is coupled to the delay circuit to generate the ramp generator input reference signal. The capacitive voltage divider includes a first variable capacitor coupled to a second variable capacitor that are tuned to provide a capacitance ratio that matches a coupling ratio from the power supply to the bitline output.

    Abstract translation: 用于读出电路的斜坡发生器包括一个积分器,该积分器被耦合以接收斜坡发生器输入参考信号,以产生耦合以由模数转换器接收的参考斜坡信号。 耦合以产生斜坡发生器输入参考信号的电源补偿电路包括延迟电路,该延迟电路包括耦合以接收电源信号的可变电阻器和滤波电容器。 调整可变电阻以匹配从电源到位线输出的延迟纹波。 电容分压器耦合到延迟电路以产生斜坡发生器输入参考信号。 电容分压器包括耦合到第二可变电容器的第一可变电容器,其被调谐以提供与从电源到位线输出的耦合比匹配的电容比。

    ADAPTIVE CORRELATED MULTIPLE SAMPLING

    公开(公告)号:US20240397226A1

    公开(公告)日:2024-11-28

    申请号:US18322431

    申请日:2023-05-23

    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

    Circuit and method for image artifact reduction in high-density, highpixel-count, image sensor with phase detection autofocus

    公开(公告)号:US11683604B1

    公开(公告)日:2023-06-20

    申请号:US17678533

    申请日:2022-02-23

    CPC classification number: H04N25/704 H04N25/11 H04N25/60

    Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

    Ramp generator providing high resolution fine gain including fractional divider with delta-sigma modulator

    公开(公告)号:US11595030B2

    公开(公告)日:2023-02-28

    申请号:US16867399

    申请日:2020-05-05

    Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

    Image sensor with frame level black level calibration

    公开(公告)号:US11206392B1

    公开(公告)日:2021-12-21

    申请号:US16931194

    申请日:2020-07-16

    Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Patent Agency Ranking