公开(公告)号：US6101580A

公开(公告)日：2000-08-08

申请号：US838971

申请日：1997-04-23

申请人： Ole Agesen ,  Steve Heller ,  Michael O'Connor ,  Guy Steele ,  Marc Tremblay

发明人： Ole Agesen ,  Steve Heller ,  Michael O'Connor ,  Guy Steele ,  Marc Tremblay

IPC分类号： G06F12/00 ,  G06F9/44 ,  G06F9/50 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F9/5016 ,  G06F12/0253 ,  G06F12/0875 ,  Y10S707/99953 ,  Y10S707/99957

摘要： In computer systems which do not inherently distinguish between references and primitive values within a program stack a method and apparatus to assist exact garbage collection techniques utilizes a stack tag cache which operates in conjunction with a program stack and supplies a tag item for every entry in the process stack. The value of a tag item indicates whether the stack entry is either a reference to another memory location or a primitive value, i.e. integer or floating point number. The arrangements and values of the tag items are correlated with changes to the program stack. The stack tag cache includes facilities for swapping the contents of the cache in the event of a trap or context switch, as well as means for redundantly verifying the tag value with intended instruction operand types.

摘要翻译： 在程序堆栈内并不固有地区分参考和原始值的计算机系统中，帮助精确垃圾收集技术的方法和装置利用与程序堆栈一起操作的栈标签高速缓存，并为 进程堆栈 标签项的值指示堆栈条目是对另一存储器位置的引用还是原始值，即整数或浮点数。 标签项的排列和值与程序堆栈的更改相关。 堆栈标签缓存包括用于在陷阱或上下文切换的情况下交换高速缓存的内容的设备，以及用于用期望的指令操作数类型冗余地验证标签值的装置。

公开(公告)号：US09619399B2

公开(公告)日：2017-04-11

申请号：US13529473

申请日：2012-06-21

申请人： Ole Agesen

发明人： Ole Agesen

IPC分类号： G06F12/02 ,  G06F12/1009

CPC分类号： G06F12/1009 ,  G06F12/1027 ,  G06F2212/152 ,  G06F2212/652 ,  G06F2212/68

摘要： A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.

公开(公告)号：US07890722B1

公开(公告)日：2011-02-15

申请号：US11099720

申请日：2005-04-06

申请人： Guy L. Steele, Jr. ,  Ole Agesen ,  Nir N. Shavit

发明人： Guy L. Steele, Jr. ,  Ole Agesen ,  Nir N. Shavit

IPC分类号： G06F12/14

CPC分类号： G06F9/524 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/30087

摘要： A sequentially performed implementation of a compound compare-and-swap (nCAS) operation has been developed. In one implementation, a double compare-and-swap (DCAS) operation does not result in a fault, interrupt, or trap in the situation where memory address A2 is invalid and the contents of memory address A1 are unequal to C1. In some realizations, memory locations addressed by a sequentially performed nCAS or DCAS instruction are reserved (e.g., locked) in a predefined order in accordance with a fixed total order of memory locations. In this way, deadlock between concurrently executed instances of sequentially performed nCAS instructions can be avoided. Other realizations defer responsibility for deadlock avoidance to the programmer.

摘要翻译： 已经开发了顺序执行的复合比较和交换（nCAS）操作。 在一个实现中，在存储器地址A2无效并且存储器地址A1的内容不等于C1的情况下，双重比较和交换（DCAS）操作不会导致故障，中断或陷阱。 在一些实现中，依次执行的nCAS或DCAS指令寻址的存储器单元根据存储单元的固定总顺序以预定义的顺序被保留（例如锁定）。 以这种方式，可以避免顺序执行的nCAS指令的同时执行的实例之间的死锁。 其他实现方式将程序员的死锁责任推迟。

公开(公告)号：US07640544B2

公开(公告)日：2009-12-29

申请号：US10996508

申请日：2004-11-23

申请人： Christine H. Flood ,  David L. Detlefs ,  Nir N. Shavit ,  Xiaolan Zhang ,  Ole Agesen

发明人： Christine H. Flood ,  David L. Detlefs ,  Nir N. Shavit ,  Xiaolan Zhang ,  Ole Agesen

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0276 ,  Y10S707/99953 ,  Y10S707/99957

摘要： A multiprocessor, multi-program, stop-the-world garbage collection program is described. The system initially over partitions the root sources, and then iteratively employs static and dynamic work balancing. Garbage collection threads compete dynamically for the initial partitions. Work stealing double-ended queues, where contention is reduced, are described to provide dynamic load balancing among the threads. Contention is resolved by using atomic instructions. The heap is broken into a young and an old generation where parallel semi-space copying is used to collect the young generation and parallel mark-compacting the old generation. Speed and efficiency of collection is enhanced by use of card tables and linking objects, and overflow conditions are efficiently handled by linking using class pointers. A garbage collection termination employs a global status word.

摘要翻译： 描述了一个多处理器，多程序，停止世界的垃圾收集程序。 系统最初对根源进行分区，然后迭代地采用静态和动态的工作平衡。 垃圾收集线程可以动态竞争初始分区。 被描述为在线程之间提供动态负载平衡的工作窃取双端队列，其中争用减少。 竞争通过使用原子指令来解决。 堆被打破成一个年轻和老一代，平行的半空间复制用于收集年轻一代和平行的标记压实老一代。 通过使用卡表和链接对象来增强收集的速度和效率，并且通过使用类指针进行链接来有效地处理溢出条件。 垃圾收集终端采用全局状态字。

公开(公告)号：US20090313445A1

公开(公告)日：2009-12-17

申请号：US12137351

申请日：2008-06-11

申请人： Vivek Pandey ,  Ole Agesen ,  Alex Garthwaite ,  Carl Waldspurger ,  Rajesh Venkatasubramanian

发明人： Vivek Pandey ,  Ole Agesen ,  Alex Garthwaite ,  Carl Waldspurger ,  Rajesh Venkatasubramanian

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F9/455 ,  G06F12/16

CPC分类号： G06F9/5033 ,  G06F9/45558 ,  G06F9/4856 ,  G06F2009/4557

摘要： A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios.

摘要翻译： 将虚拟机的存储器从一个NUMA节点迁移到另一个NUMA节点的系统和相关操作方法。 一旦将VM迁移到新节点，就会在优先使用最多的页面的同时执行内存页面的迁移，以便尽快访问这些页面。 描述了各种启发式方法，以实现不同情况或场景的不同实现。

公开(公告)号：US07487314B1

公开(公告)日：2009-02-03

申请号：US11865658

申请日：2007-10-01

申请人： Ole Agesen ,  Jeffrey W. Sheldon

发明人： Ole Agesen ,  Jeffrey W. Sheldon

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/1475 ,  G06F2212/656

摘要： A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

公开(公告)号：US07281102B1

公开(公告)日：2007-10-09

申请号：US10917713

申请日：2004-08-12

申请人： Ole Agesen ,  Jeffrey W. Sheldon

发明人： Ole Agesen ,  Jeffrey W. Sheldon

IPC分类号： G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/656

摘要： A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

公开(公告)号：US07277999B1

公开(公告)日：2007-10-02

申请号：US10918044

申请日：2004-08-12

申请人： Ole Agesen ,  Jeffrey W. Sheldon

发明人： Ole Agesen ,  Jeffrey W. Sheldon

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/1475 ,  G06F2212/656

摘要： A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

公开(公告)号：US07222221B1

公开(公告)日：2007-05-22

申请号：US10774095

申请日：2004-02-06

申请人： Ole Agesen ,  Pratap Subrahmanyam ,  Keith M. Adams

发明人： Ole Agesen ,  Pratap Subrahmanyam ,  Keith M. Adams

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F9/45537 ,  G06F9/45558 ,  G06F12/0292 ,  G06F2009/45583 ,  G06F2212/682 ,  Y10S707/99952

摘要： A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

摘要翻译： 计算机系统具有从主数据导出的辅助数据，诸如从页表中的条目导出的TLB中的条目。 当演员改变主要数据时，制片人指示在生产者和消费者共享的存储器中的设置数据结构（例如数据阵列）中的改变。 可能有多个生产者和多个消费者，每个生产者/消费者对都有一个单独的渠道。 在一致性事件中，应删除主数据和辅助数据之间的货币，消费者读取通道以确定更改，并相应地更新次要数据。 该系统可以是多处理器虚拟计算机系统，该演员可以是客户操作系统，并且生产者和消费者可以是虚拟机监视器内的子系统，其中每个子系统导出单独的虚拟中央处理单元。

公开(公告)号：US07149843B1

公开(公告)日：2006-12-12

申请号：US11185151

申请日：2005-07-19

申请人： Ole Agesen ,  Pratap Subrahmanyam ,  Scott W. Devine ,  Mendel Rosenblum ,  Edouard Bugnion

发明人： Ole Agesen ,  Pratap Subrahmanyam ,  Scott W. Devine ,  Mendel Rosenblum ,  Edouard Bugnion

IPC分类号： G06F13/00

CPC分类号： G06F9/45537 ,  G06F9/4812

摘要： A computer system includes at least one virtual machine that has a plurality of virtual processors all running on an underlying hardware platform. A software interface layer such as a virtual machine monitor establishes traces on primary structures located in a common memory space as needed for the different virtual processors. Whenever any one of the virtual processors generates a trace event, such as accessing a traced structure, then a notification is sent to at least the other virtual processors that have a trace on the accessed primary structure. In some applications, the VMM derives and maintains secondary structures corresponding to the primary structures, such as where the VMM converts, through binary translation, original code intended to run on a virtual processor into code that can be run on an underlying physical processor of the hardware platform. In these applications, the VMM may rederive or invalidate the secondary structures as needed upon receipt of the notification of the trace event. Different semantics are provided for the notification, providing different choices of performance versus guaranteed consistency between primary and secondary structures. In the preferred embodiment of the invention, a dedicated sub-system is included within the VMM for each virtual processor; each sub-system establishes traces, senses trace events, issues the notification, and performs other operations relating specifically to its respective virtual processor.

摘要翻译： 计算机系统包括至少一个具有在底层硬件平台上运行的多个虚拟处理器的虚拟机。 诸如虚拟机监视器之类的软件接口层根据不同虚拟处理器的需要，在位于公共存储器空间中的主结构上建立迹线。 无论何时任何一个虚拟处理器生成跟踪事件（例如访问跟踪结构），则向至少在所访问的主要结构上具有跟踪的其他虚拟处理器发送通知。 在某些应用中，VMM导出和维护对应于主要结构的二级结构，例如VMM通过二进制转换将旨在在虚拟处理器上运行的原始代码转换为可以在底层物理处理器上运行的代码 硬件平台。 在这些应用中，VMM可以在接收到跟踪事件的通知时根据需要重新激活或使二级结构无效。 为通知提供不同的语义，提供不同的性能选择与主要和次要结构之间的一致性保证。 在本发明的优选实施例中，专用子系统包括在每个虚拟处理器的VMM内; 每个子系统建立跟踪，感测跟踪事件，发出通知，并执行与其各自的虚拟处理器专门相关的其他操作。