公开(公告)号：US20180041723A1

公开(公告)日：2018-02-08

申请号：US15228874

申请日：2016-08-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Keiji Mabuchi ,  Dyson H. Tai ,  Oray Orkun Cellek ,  Duli Mao ,  Sohei Manabe

IPC: H04N5/355 ,  H01L27/146 ,  H04N9/04 ,  H04N5/378 ,  H04N5/3745

Abstract: A pixel array for use in a high dynamic range image sensor includes a plurality of pixels arranged in a plurality of rows and columns in the pixel array. Each one of the pixels includes a linear subpixel and a log subpixel disposed in a semiconductor material. The linear subpixel is coupled to generate a linear output signal having a linear response, and the log subpixel is coupled to generate a log output signal having a logarithmic response in response to the incident light. A bitline is coupled to the linear subpixel and to the log subpixel to receive the linear output signal and the log output signal. The bitline is one of a plurality of bitlines coupled to the plurality of pixels. Each one of the plurality of bitlines is coupled to a corresponding grouping of the plurality of pixels.

公开(公告)号：US20170180663A1

公开(公告)日：2017-06-22

申请号：US14979058

申请日：2015-12-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Keiji Mabuchi ,  Sohei Manabe

IPC: H04N5/378 ,  H04N5/353 ,  H04N5/374

CPC classification number: H04N5/37455 ,  H01L27/14634 ,  H04N5/345 ,  H04N5/369 ,  H04N5/374 ,  H04N5/378

Abstract: High speed rolling image sensor includes pixel array disposed in first semiconductor die, readout circuits disposed in second semiconductor die and conductors. Pixel array is partitioned into pixel sub-arrays (PSAs). Each of the PSAs includes a plurality of pixels. Pixel groups include pixels that are non-contiguous, non-overlapping and distinct. Each pixel group includes pixels from different PSAs. Each pixel group is coupled to a corresponding analog-to-digital converter and memory unit tiles (ADMs) respectively included in readout circuits. ADMs respectively include (i) analog-to-digital (ADC) circuits that convert the image data from pixel groups from analog to digital to obtain ADC outputs, and (ii) memory units to store ADC outputs. Conductors are coupling pixel array to ADMs. Conductors include number of conductors per column of pixel array. Number of conductors per column of pixel array may be equal to number of pixels in PSA arranged in same column. Other embodiments are described.

公开(公告)号：US09391111B1

公开(公告)日：2016-07-12

申请号：US14820992

申请日：2015-08-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Keiji Mabuchi ,  Chih-Wei Hsiung

IPC: H01L23/02 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14601 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645

Abstract: An intermediate integrated circuit die of a stacked integrated circuit system includes an intermediate semiconductor substrate including first polarity dopants is thinned from a second side. A first well including first polarity dopants is disposed in the intermediate semiconductor proximate to a first side. A second well including second polarity dopants is disposed in the intermediate semiconductor substrate proximate to the first side. A deep well having second polarity dopants is disposed in the intermediate semiconductor substrate beneath the first and second wells. An additional implant of first polarity dopants is implanted into the intermediate semiconductor substrate between the deep well and the second side of the intermediate semiconductor substrate to narrow a depletion region overlapped by the additional implant of first polarity dopants. The depletion region is between the deep well and the second side of the intermediate semiconductor substrate.

Abstract translation: 堆叠集成电路系统的中间集成电路管芯包括中间半导体衬底，其包括第一极性掺杂剂从第二侧变薄。 包括第一极性掺杂剂的第一阱设置在靠近第一侧的中间半导体中。 包括第二极性掺杂剂的第二阱设置在靠近第一侧的中间半导体衬底中。 具有第二极性掺杂剂的深井设置在第一和第二阱下面的中间半导体衬底中。 将第一极性掺杂剂的另外的注入植入到中间半导体衬底的深阱和第二侧之间的中间半导体衬底中，以缩小由第一极性掺杂剂的附加注入重叠的耗尽区。 耗尽区位于中间半导体衬底的深阱和第二侧之间。

公开(公告)号：US20250081640A1

公开(公告)日：2025-03-06

申请号：US18456659

申请日：2023-08-28

Applicant: OmniVision Technologies, Inc.

Inventor： Yoshiyuki Matsunaga ,  Cynthia Lee ,  Keiji Mabuchi ,  Lindsay Grant

IPC: H01L27/146

Abstract: A pixel circuit including a transistor, a blocking layer and an output circuit is disclosed. The transistor includes a first doped region and a second doped region disposed on opposite sides of a channel of the transistor proximate to a first surface of a semiconductor substrate such that photo-carriers generated inside the semiconductor substrate in response to incident light flow into one region of the first and second doped regions. The blocking layer is disposed between the other region of the first and second doped regions and a second surface of the semiconductor substrate opposite to the first surface. The blocking layer configured to block the photo-carriers from flowing into the other region of the first doped region and the second doped region directly. The output circuit outputs an image signal according to a voltage signal outputted from the transistor.

公开(公告)号：US20220320163A1

公开(公告)日：2022-10-06

申请号：US17217937

申请日：2021-03-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun ,  Yibo Zhu ,  Keiji Mabuchi

IPC: H01L27/146

Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.

公开(公告)号：US11356626B2

公开(公告)日：2022-06-07

申请号：US16855850

申请日：2020-04-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Eiichi Funatsu ,  Woon Il Choi ,  Keiji Mabuchi ,  Chin Poh Pang ,  Qingfei Chen ,  Da Meng ,  Vivian Wang

IPC: H04N5/369 ,  H01L27/146 ,  H04N5/355 ,  H04N5/378

Abstract: An imaging device includes a photodiode array. The photodiodes include a first set of photodiodes configured as image sensing photodiodes and a second set of photodiodes configured as phase detection auto focus (PDAF) photodiodes. The PDAF photodiodes are arranged in at least pairs in neighboring columns and are interspersed among the image sensing photodiodes. Transfer transistors are coupled to corresponding photodiodes. The transfer transistors coupled to the image sensing photodiodes included in an active row of are controlled in response to a first transfer control signal or a second transfer control signal that control all of the image sensing photodiodes of the active row. A transfer transistor is coupled to one of a pair of the PDAF photodiodes of the active row. The first transfer transistor is controlled in response to a first PDAF control signal that is independent of the first or second transfer control signals.

公开(公告)号：US11211421B2

公开(公告)日：2021-12-28

申请号：US16255194

申请日：2019-01-23

Applicant: OmniVision Technologies, Inc.

Inventor： Xianmin Yi ,  Jingming Yao ,  Philip Cizdziel ,  Eric Webster ,  Duli Mao ,  Zhiqiang Lin ,  Jens Landgraf ,  Keiji Mabuchi ,  Kevin Johnson ,  Sohei Manabe ,  Dyson H. Tai ,  Lindsay Grant ,  Boyd Fowler

IPC: G01S17/89 ,  H01L27/146 ,  H01L31/107 ,  H01L31/02 ,  H01L27/148 ,  G01S17/10

Abstract: A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit.

公开(公告)号：US11196950B2

公开(公告)日：2021-12-07

申请号：US16506693

申请日：2019-07-09

Applicant: OmniVision Technologies, Inc.

Inventor： Keiji Mabuchi ,  Sohei Manabe ,  Lindsay Grant

IPC: H04N5/357 ,  H04N5/374 ,  H04N5/369 ,  H04N5/361 ,  H04N5/3745 ,  H04N5/378

Abstract: An image sensor has an array of pixels, each pixel having an associated shutter transistor coupled to transfer a charge dependent on light exposure of the pixel onto an image storage capacitor, the image-storage capacitors being configured to be read into an analog to digital converter. The shutter transistors are P-type transistors in N-wells, the wells held at an analog power voltage to reduce sensitivity of pixels to dark current; in an alternative embodiment the shutter transistors are N-type transistors in P-wells, the wells held at an analog ground voltage.

公开(公告)号：US20210337144A1

公开(公告)日：2021-10-28

申请号：US16855850

申请日：2020-04-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Eiichi Funatsu ,  Woon Il Choi ,  Keiji Mabuchi ,  Chin Poh Pang ,  Qingfei Chen ,  Da Meng ,  Vivian Wang

IPC: H04N5/369 ,  H01L27/146 ,  H04N5/355 ,  H04N5/378

Abstract: An imaging device includes a photodiode array. The photodiodes include a first set of photodiodes configured as image sensing photodiodes and a second set of photodiodes configured as phase detection auto focus (PDAF) photodiodes. The PDAF photodiodes are arranged in at least pairs in neighboring columns and are interspersed among the image sensing photodiodes. Transfer transistors are coupled to corresponding photodiodes. The transfer transistors coupled to the image sensing photodiodes included in an active row of are controlled in response to a first transfer control signal or a second transfer control signal that control all of the image sensing photodiodes of the active row. A transfer transistor is coupled to one of a pair of the PDAF photodiodes of the active row. The first transfer transistor is controlled in response to a first PDAF control signal that is independent of the first or second transfer control signals.

公开(公告)号：US11095842B2

公开(公告)日：2021-08-17

申请号：US16523850

申请日：2019-07-26

Applicant: OmniVision Technologies, Inc.

Inventor： Keiji Mabuchi ,  Sohei Manabe ,  Lindsay Grant

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/378 ,  H04N5/357

Abstract: An image sensor has an array of pixel blocks, and each pixel block having associated shutter transistors with each coupled to transfer an image signal comprising a charge dependent on light exposure of a selected pixel onto an image storage capacitor of a plurality of image storage capacitors associated with the pixel block, the image storage capacitors of the pixel block configured to be read through a differential amplifier into an analog to digital converter. The differential amplifier of each pixel block receives a second input from a single reset-sampling capacitor associated with the pixel block. The single reset-sampling capacitor is loaded when the pixels of the pixel block are reset.