公开(公告)号：US06813274B1

公开(公告)日：2004-11-02

申请号：US09532341

申请日：2000-03-21

Applicant: Hiroshi Suzuki ,  Paul Chang ,  Sharat Prasad ,  Chien Fang

Inventor： Hiroshi Suzuki ,  Paul Chang ,  Sharat Prasad ,  Chien Fang

IPC: H04L1220

CPC classification number: H04L49/101 ,  H04L49/1576 ,  H04L49/3018

Abstract: A network switch and a method for data switching using a crossbar switch fabric with output port groups operating concurrently and independently that increases throughput and reduces scheduling complexity. The network switch includes a crossbar switch fabric, plurality of output port groups, and a plurality of input ports. The crossbar switch fabric includes a plurality of inputs and outputs. The plurality of output port groups operate concurrently and independently, and each output port group includes one or more output ports and is configured to receive a packet from one of the outputs of the crossbar switch and to send the packet to an output port. The plurality of input ports are coupled to an input of the crossbar switch fabric and configured to send packets to the crossbar switch fabric through the input of the crossbar switch fabric. Each input port includes a plurality of input buffer groups, and each input buffer group is assigned to send a packet for one of the output port groups such that there is a one-to-one correspondence between each of the input buffer groups and output port groups.

Abstract translation: 一种网络交换机和一种使用交叉开关结构进行数据交换的方法，输出端口组同时且独立地运行，从而增加吞吐量并降低调度复杂度。 网络交换机包括交叉开关结构，多个输出端口组以及多个输入端口。 交叉开关结构包括多个输入和输出。 多个输出端口组并行且独立地操作，并且每个输出端口组包括一个或多个输出端口，并且被配置为从交叉开关的输出之一接收分组，并将分组发送到输出端口。 多个输入端口耦合到交叉开关结构的输入端并且被配置为通过交叉开关结构的输入将分组发送到交叉开关结构。 每个输入端口包括多个输入缓冲器组，并且每个输入缓冲器组被分配以发送一个输出端口组的分组，使得每个输入缓冲器组和输出端口之间存在一一对应关系 团体

公开(公告)号：US06420225B1

公开(公告)日：2002-07-16

申请号：US09805815

申请日：2001-03-13

Applicant: Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

Inventor： Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

IPC: H01L218234

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract translation: 一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域 主要表面毗邻门。 第二导电类型的多个通道各自邻接源/漏区并在栅极下方延伸。

公开(公告)号：US06331455B1

公开(公告)日：2001-12-18

申请号：US09283537

申请日：1999-04-01

Applicant: Vladimir Rodov ,  Wayne Y. W. Hsueh ,  Paul Chang ,  Michael Chern

Inventor： Vladimir Rodov ,  Wayne Y. W. Hsueh ,  Paul Chang ,  Michael Chern

IPC: H01L21332

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861 ,  H01L29/872

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells. The present invention further provides a method for manufacturing a rectifier device which provides highly repeatable device characteristics and which can provide such devices at reduced cost. The active channel regions of the device are defined using pedestals in a double spacer, double implant self-aligned process. The channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer sidewall formation. Only two masking steps are required, reducing processing costs.

Abstract translation: 具有低导通电阻，质量恢复时间和低正向压降的电力整流器。 在优选实施例中，本发明提供一种采用垂直装置结构的电力整流装置，即在分立装置主要表面之间的电流流动。 该器件采用大量并联连接的单元，每个单元包括具有栅极的MOSFET结构，以通过公共金属化来短路。 这提供了通过MOSFET单元的沟道区域到集成电路另一侧的源极区域的低Vf路径。 薄栅结构围绕设备的上表面上的基座区域环形地形成，并且精确控制的体植入物限定沟道区域并且允许可控制的器件特性，包括栅极阈值电压和Vf。 还提供了并联肖特基二极管，其提高了MOSFET电池的开关速度。 本发明还提供一种制造整流器件的方法，其提供高度可重复的器件特性，并且可以以降低的成本提供这样的器件。 器件的有源通道区域使用双间隔器中的基座来限定，双注入自对准过程。 尽管间隔壁侧壁形成中不可避免的工艺变化也可精确地控制通道尺寸和掺杂特性。 只需要两个屏蔽步骤，降低处理成本。

公开(公告)号：US5448565A

公开(公告)日：1995-09-05

申请号：US975236

申请日：1992-11-12

Applicant: Paul Chang ,  Joseph W. Coates ,  Edward H. C. Ku ,  Simin H. Sanaye

Inventor： Paul Chang ,  Joseph W. Coates ,  Edward H. C. Ku ,  Simin H. Sanaye

IPC: H04L12/46

CPC classification number: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller, a Packet Memory and a Transparent Bridge Control Management System (TBCMS). Each Bridge Port Frame Handler unit receives Frames from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handler Units for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

Abstract translation: 多端口桥接器包括通过源路由总线和透明桥接总线耦合到微控制器，分组存储器和透明网桥控制管理系统（TBCMS）的多个桥接端口帧处理器（BPFH）单元。 每个桥接端口帧处理器单元从其连接的LAN接收帧，将源路由帧的选定部分转发到其他网桥端口帧处理单元进行进一步处理。 同样地，将透明网桥帧的选定部分转发到TBCMS，在该TBCMS中提取路由信息和签名信息，并返回到转发BPFH单元进行进一步处理。

公开(公告)号：US4331756A

公开(公告)日：1982-05-25

申请号：US203881

申请日：1980-11-04

Applicant: Edward F. Mayer ,  Arthur S. Diamond ,  Paul Chang

Inventor： Edward F. Mayer ,  Arthur S. Diamond ,  Paul Chang

IPC: G03G9/10 ,  G03G9/113

CPC classification number: G03G9/1135 ,  G03G9/10 ,  G03G9/1133

Abstract: Electrophotographic developer compositions containing carrier, toner and special purpose additives such as flow promoters, dry lubricants and the like are prepared by coating carrier particles with a coating selected so that the triboelectric relationship between the surface of the carrier and the surface of the additive is substantially zero.

Abstract translation: 包含载体，调色剂和特殊用途添加剂如流动促进剂，干性润滑剂等的电子照相显影剂组合物通过涂布载体颗粒来制备，所述涂层选择为使得载体表面和添加剂表面之间的摩擦关系基本上 零。

公开(公告)号：US09024355B2

公开(公告)日：2015-05-05

申请号：US13483200

申请日：2012-05-30

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Abstract translation: 翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。 在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。 使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。 通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。 在形成平坦化介电层之后，去除一次性栅极结构。 使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。 在多个半导体鳍片上形成替换栅极结构。

公开(公告)号：US08981478B2

公开(公告)日：2015-03-17

申请号：US13611335

申请日：2012-09-12

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.

Abstract translation: 半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分 蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。

公开(公告)号：US08949080B2

公开(公告)日：2015-02-03

申请号：US12862991

申请日：2010-08-25

Applicant: Kuo-Tsai Li ,  Paul Chang ,  Andy Chang

Inventor： Kuo-Tsai Li ,  Paul Chang ,  Andy Chang

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068 ,  G06F17/5081

Abstract: A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.

Abstract translation: 集成电路的设计方法包括执行集成电路的预布局仿真。 使用从过程设计工具包（PDK）文件生成的网表执行预布局模拟。 PDK文件包括分配给多个设备的多个设备模型卡。 多个器件包括具有至少一个与至少一个隔离阱相关联的寄生二极管的第一器件，该PDK文件包括至少一个寄生二极管的信息。 生成对应于预布局仿真结果的集成电路的设计布局。

公开(公告)号：US20130320399A1

公开(公告)日：2013-12-05

申请号：US13483200

申请日：2012-05-30

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66484 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Abstract translation: 翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。 在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。 使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。 通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。 在形成平坦化介电层之后，去除一次性栅极结构。 使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。 在多个半导体鳍片上形成替换栅极结构。

公开(公告)号：US20130214357A1

公开(公告)日：2013-08-22

申请号：US13398339

申请日：2012-02-16

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-hsun Lin ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/0657 ,  H01L29/66795

Abstract: Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.

Abstract translation: 非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。 这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。 剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。 因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。 所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。 鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。