公开(公告)号：US20090256590A1

公开(公告)日：2009-10-15

申请号：US12100406

申请日：2008-04-10

Applicant: Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

Inventor： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC: H03K19/0944 ,  G11C16/04

CPC classification number: H03K17/693 ,  G11C16/0433 ,  G11C16/26

Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

Abstract translation: 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。第一和第二非易失性存储器单元中的每一个用于存储与另一个相反的状态。 复用器具有输入，开关输入和两个输出。 输出节点连接到多路复用器的输入。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US07321493B2

公开(公告)日：2008-01-22

申请号：US11079810

申请日：2005-03-14

Applicant: Hsing-Sheng Liang ,  George Sya ,  Hong Huynh ,  Michael Koken ,  Michael Chern ,  Yuan-Cheng Fang

Inventor： Hsing-Sheng Liang ,  George Sya ,  Hong Huynh ,  Michael Koken ,  Michael Chern ,  Yuan-Cheng Fang

IPC: H05K7/20

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved heatsink attachment assembly includes a first anchor configured to secure to a first location of the circuit board, and a second anchor configured to secure to a second location of the circuit board. Each anchor includes legs having looped end portions configured to contact the circuit board. The heatsink attachment assembly further includes a heatsink clip configured to concurrently (i) fasten to the anchors when the anchors secure to the circuit board, and (ii) hold a heatsink to against a circuit board component of the circuit board. The looped end portions of the legs prevent the legs from completely passing through holes defined in the circuit board. In some situations, the looped end portions define extended coils (e.g., double loops) for a robust interference fit with the circuit board as well as for enhanced strength and stability.

Abstract translation: 改进的散热器连接组件包括被配置为固定到电路板的第一位置的第一锚固件和被配置成固定到电路板的第二位置的第二锚固件。 每个锚杆包括腿部，腿部具有被配置为接触电路板的环形端部。 散热器连接组件还包括散热夹，该散热夹构造成当锚固件固定到电路板上时同时（i）固定到锚固件，以及（ii）将散热片固定在电路板的电路板部件上。 腿的环形端部防止腿部完全穿过限定在电路板中的孔。 在一些情况下，环形端部限定用于与电路板的鲁棒干涉配合以及用于增强强度和稳定性的延伸线圈（例如，双环）。

公开(公告)号：US07292456B2

公开(公告)日：2007-11-06

申请号：US11274024

申请日：2005-11-15

Applicant: Jimmy Leung ,  Mandy Lam ,  Toan Nguyen ,  Saeed Seyed ,  Michael Chern

Inventor： Jimmy Leung ,  Mandy Lam ,  Toan Nguyen ,  Saeed Seyed ,  Michael Chern

IPC: H05K7/12

CPC classification number: H05K7/1409

Abstract: A control assembly controls removal of a circuit board from a chassis. The control assembly includes a support member configured to fasten to the circuit board, and a handle pivotally attached to the support member. The handle is configured to swing from an opened position to a closed position relative to the support member during installation of the circuit board within the chassis, and from the closed position to the opened position during removal of the circuit board from the chassis. The control assembly further includes a button configured to move between a biased position and a depressed position relative to the support member. The button is further configured to (i) inhibit removal of the circuit board from the chassis when the button is in the biased position, and (ii) enable removal of the circuit board from the chassis when the button is in the depressed position.

Abstract translation: 控制组件控制电路板从机箱的移除。 控制组件包括构造成紧固到电路板的支撑构件和可枢转地附接到支撑构件的手柄。 手柄被构造成在将电路板安装在底盘内时从相对于支撑构件的打开位置摆动到闭合位置，并且在将电路板从底盘移除期间从关闭位置转动到打开位置。 所述控制组件还包括按钮，所述按钮被配置为相对于所述支撑构件在偏置位置和凹陷位置之间移动。 该按钮还被配置为（i）当按钮处于偏置位置时，禁止从底盘移除电路板，以及（ii）当按钮处于按压位置时，使得能够从底盘移除电路板。

公开(公告)号：US06856511B1

公开(公告)日：2005-02-15

申请号：US10621836

申请日：2003-07-17

Applicant: Rainier Viernes ,  Michael Chern

Inventor： Rainier Viernes ,  Michael Chern

IPC: H01L23/40 ,  H05K7/20

CPC classification number: H01L23/4093 ,  H01L2224/16

Abstract: A retainer directly attaches to a circuit board component and to a heat sink and secures the circuit board component to the heat sink. The retainer provides a mechanical attachment between the heat sink and the circuit board component. Such mechanical attachment maintains thermal communication between the heat sink and the circuit board component in the absence of a thermally conductive adhesive between the heat sink and the circuit board component for the operational life of the circuit board component. Furthermore, because the retainer attaches directly to the circuit board component and to the heat sink, the retainer minimizes the necessity for use of mounting holes in the circuit board associated with the circuit board component to secure the heat sink to the circuit board component.

Abstract translation: 保持器直接连接到电路板部件和散热器，并将电路板部件固定到散热器。 保持器在散热器和电路板部件之间提供机械连接。 在电路板部件的使用寿命期间，这种机械连接在散热器和电路板部件之间没有导热粘合剂的情况下保持散热器和电路板部件之间的热连通。 此外，由于保持器直接连接到电路板部件和散热器，所以保持器最小化在与电路板部件相关联的电路板中使用安装孔的必要性，以将散热器固定到电路板部件。

公开(公告)号：US06186408B1

公开(公告)日：2001-02-13

申请号：US09322269

申请日：1999-05-28

Applicant: Vladimir Rodov ,  Wayne Y. W. Hsueh ,  Paul Chang ,  Michael Chern

Inventor： Vladimir Rodov ,  Wayne Y. W. Hsueh ,  Paul Chang ,  Michael Chern

IPC: H01L21336

CPC classification number: H01L29/861 ,  H01L27/0814 ,  H01L27/095

Abstract: A power rectifier having low on resistance, fast recovery times and very low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. A self aligned body implant and a shallow silicide drain contact region integrated with a metal silicide drain contact define a narrow channel region and allow very high cell density. This provides a low Vf path through the channel regions of the MOSFET cells to the contact on the other side of the integrated circuit. The present invention further provides a method for manufacturing a rectifier device which provides the above desirable device characteristics in a repeatable manner. Also, only two masking steps are required, reducing processing costs.

Abstract translation: 具有导通电阻低，快速恢复时间和非常低的正向压降的电力整流器。 在优选实施例中，本发明提供一种采用垂直装置结构的电力整流装置，即在分立装置主要表面之间的电流流动。 该器件采用大量并联连接的单元，每个单元包括具有栅极的MOSFET结构，以通过公共金属化来短路。 与金属硅化物漏极接触点整合的自对准体植入物和浅硅化物漏极接触区域限定窄通道区域并且允许非常高的细胞密度。 这提供了通过MOSFET单元的沟道区域到集成电路另一侧上的触点的低Vf路径。 本发明还提供了一种用于制造以可重复的方式提供上述所需装置特性的整流装置的方法。 此外，只需要两个屏蔽步骤，从而降低处理成本。

公开(公告)号：US07874869B2

公开(公告)日：2011-01-25

申请号：US12411444

申请日：2009-03-26

Applicant: Michael Chern ,  Saeed Seyed ,  Tung Po Yang

Inventor： Michael Chern ,  Saeed Seyed ,  Tung Po Yang

IPC: H01R13/73 ,  H02B1/01

CPC classification number: H01R13/518 ,  H04Q1/131 ,  Y10T29/53209

Abstract: A reconfigurable patch panel and a method of reconfiguring a patch panel comprising a support member supporting at least one adapter, where the at least one adapter comprises a plurality of ports for coupling to electric signal bearing cables. A pivot, associated with each of the at least one adapters, couples the at least one adapter to the support member. The at least one adapter selectively rotates about the pivot to a selected position relative to the support member. A retainer, associated with each of the at least one adapters, couples the support member to the at least one adapter and retains the at least one adapter in the selected position.

Abstract translation: 一种可重构接线板和重新配置接线板的方法，其包括支撑至少一个适配器的支撑构件，其中所述至少一个适配器包括用于耦合到电信号轴承电缆的多个端口。 与所述至少一个适配器中的每一个相关联的枢轴将所述至少一个适配器耦合到所述支撑构件。 所述至少一个适配器选择性地围绕所述枢轴旋转到相对于所述支撑构件的选定位置。 与所述至少一个适配器中的每一个相关联的保持器将所述支撑构件联接到所述至少一个适配器并将所述至少一个适配器保持在所选择的位置。

公开(公告)号：US20100248535A1

公开(公告)日：2010-09-30

申请号：US12411444

申请日：2009-03-26

Applicant: Michael Chern ,  Saeed Seved ,  Tung Po Yang

Inventor： Michael Chern ,  Saeed Seved ,  Tung Po Yang

IPC: H01R13/514 ,  H01R43/20

CPC classification number: H01R13/518 ,  H04Q1/131 ,  Y10T29/53209

Abstract: A reconfigurable patch panel and a method of reconfiguring a patch panel comprising a support member supporting at least one adapter, where the at least one adapter comprises a plurality of ports for coupling to electric signal bearing cables. A pivot, associated with each of the at least one adapters, couples the at least one adapter to the support member. The at least one adapter selectively rotates about the pivot to a selected position relative to the support member. A retainer, associated with each of the at least one adapters, couples the support member to the at least one adapter and retains the at least one adapter in the selected position.

Abstract translation: 一种可重构接线板和重新配置接线板的方法，其包括支撑至少一个适配器的支撑构件，其中所述至少一个适配器包括用于耦合到电信号轴承电缆的多个端口。 与所述至少一个适配器中的每一个相关联的枢轴将所述至少一个适配器耦合到所述支撑构件。 所述至少一个适配器选择性地围绕所述枢轴旋转到相对于所述支撑构件的选定位置。 与所述至少一个适配器中的每一个相关联的保持器将所述支撑构件联接到所述至少一个适配器并将所述至少一个适配器保持在所选择的位置。

公开(公告)号：US07701248B2

公开(公告)日：2010-04-20

申请号：US12100406

申请日：2008-04-10

Applicant: Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

Inventor： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC: G06F7/38 ,  H03K19/173 ,  G11C7/00

CPC classification number: H03K17/693 ,  G11C16/0433 ,  G11C16/26

Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

Abstract translation: 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。 第一和第二非易失性存储单元中的每一个用于存储与另一个相反的状态。 解复用器具有输入，开关输入和两个输出。 输出节点连接到解复用器的输入端。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US20090201744A1

公开(公告)日：2009-08-13

申请号：US12027654

申请日：2008-02-07

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07974136B2

公开(公告)日：2011-07-05

申请号：US12645337

申请日：2009-12-22

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

IPC: G11C16/04

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。