公开(公告)号：US20070006010A1

公开(公告)日：2007-01-04

申请号：US11170887

申请日：2005-06-30

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F1/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

摘要翻译： 提供了同步信号发生器，其包含第一和第二计数和延迟电路，它们都相对于复位信号同步/延迟电路处于分层位置。 复位信号同步/延迟电路和第一和第二计数和延迟电路由基本时钟信号或从其导出的第一时钟信号在频率和相位上相同，并且包含计数装置，其初始和最终计数状态是可调节的 为了以时钟方式设置由第一计数和延迟电路输出的第一和第二负载信号的时间位置以及由第二计数和延迟电路输出的FIFO读取时钟信号，以及 从而使它们适应包含同步信号发生器的半导体存储器系统的时间要求。

公开(公告)号：US07633814B2

公开(公告)日：2009-12-15

申请号：US11735928

申请日：2007-04-16

申请人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

发明人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

IPC分类号： G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

摘要翻译： 一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。

公开(公告)号：US07523250B2

公开(公告)日：2009-04-21

申请号：US11509092

申请日：2006-08-24

申请人： Paul Wallner ,  Andre Schäfer ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schäfer ,  Peter Gregorius

IPC分类号： G06F11/14 ,  G06F13/28

CPC分类号： G11C8/12 ,  G11C7/1051 ,  G11C2207/107

摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控​​制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。

公开(公告)号：US07515075B1

公开(公告)日：2009-04-07

申请号：US11856353

申请日：2007-09-17

申请人： Paul Wallner ,  Chaitanya Dudha ,  Peter Gregorius ,  Masthan Devalla

发明人： Paul Wallner ,  Chaitanya Dudha ,  Peter Gregorius ,  Masthan Devalla

IPC分类号： H03M9/00

CPC分类号： G06F5/06 ,  H03K5/135 ,  H03M9/00

摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。

公开(公告)号：US20090073010A1

公开(公告)日：2009-03-19

申请号：US11856353

申请日：2007-09-17

申请人： Paul Wallner ,  Chaitanya Dudha ,  Peter Gregorius ,  Masthan Devalla

发明人： Paul Wallner ,  Chaitanya Dudha ,  Peter Gregorius ,  Masthan Devalla

IPC分类号： H03M9/00

CPC分类号： G06F5/06 ,  H03K5/135 ,  H03M9/00

摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。

公开(公告)号：US07391657B2

公开(公告)日：2008-06-24

申请号：US11751984

申请日：2007-05-22

申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C11/4096

摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。

公开(公告)号：US07313211B2

公开(公告)日：2007-12-25

申请号：US10407033

申请日：2003-04-03

申请人： Peter Gregorius ,  Edoardo Prete ,  Paul Wallner

发明人： Peter Gregorius ,  Edoardo Prete ,  Paul Wallner

IPC分类号： H03D3/24

CPC分类号： H03L7/091 ,  H04L7/0083 ,  H04L7/033

摘要： The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.

摘要翻译： 本发明涉及根据两个周期信号之间的相位差产生输出信号的方法和装置。 本发明在锁相环和延迟锁定环特别有用，其中基于通过相位检测确定的相位差来控制可控振荡器或可控延迟器件，使得控制信号可以 获得，相位滞后或其频率与参考信号具有牢固的关系。

公开(公告)号：US20070280007A1

公开(公告)日：2007-12-06

申请号：US11735971

申请日：2007-04-16

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device comprising a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

摘要翻译： 一种存储器件，包括存储单元阵列; 输入电路，其根据外部接收到的命令数据向存储单元阵列提供驱动信号; 缓冲从存储单元阵列读出的数据的输出缓冲器; 以及驱动输出缓冲器的定时器，使得缓冲的数据在经过可调整时间间隔之后的输出处提供，可调整的时间间隔从提供驱动信号开始。

公开(公告)号：US20070217268A1

公开(公告)日：2007-09-20

申请号：US11751984

申请日：2007-05-22

申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C11/4096

摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于对包括在一个或多个帧中的一个或多个命令进行解码，并将数据地址，命令和读/写访问指示信号输出到存储器核心和 中间数据缓冲区。

公开(公告)号：US20070091711A1

公开(公告)日：2007-04-26

申请号：US11259376

申请日：2005-10-26

申请人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C8/18

摘要： Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

摘要翻译： 用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。 数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。 附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。