公开(公告)号：US06485945B1

公开(公告)日：2002-11-26

申请号：US09444214

申请日：1999-11-19

申请人： Richard C. Potter ,  Philip A. Fisher ,  Kirk R. Hash, Sr. ,  John D. Neidt

发明人： Richard C. Potter ,  Philip A. Fisher ,  Kirk R. Hash, Sr. ,  John D. Neidt

IPC分类号： C12P1904

CPC分类号： C08B37/0003 ,  C08B37/0024

摘要： An entirely aqueous method for concentrating water soluble polysaccharides having molecular weights of at least about 50 kDa. The method comprises evaporating a water soluble polysaccharide-containing solution until surface film formation occurs, and harvesting the resulting film which is enriched in the polysaccharide. The polysaccharide may be of plant or animal origin, and includes polysaccharides such as guar gum, xanthan gum and pectin.

摘要翻译： 用于浓缩分子量至少约为50kDa的水溶性多糖的完全水性方法。 该方法包括蒸发含水溶性多糖的溶液直到发生表面成膜，并且收获富含多糖的所得膜。 多糖可以是植物或动物来源的，并且包括多糖如瓜尔胶，黄原胶和果胶。

公开(公告)号：US06391733B1

公开(公告)日：2002-05-21

申请号：US09849646

申请日：2001-05-04

申请人： Philip A. Fisher

发明人： Philip A. Fisher

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  Y10S438/923

摘要： A method of making a semiconductor device includes performing a doping implant through a layer of dielectric material. The implanting through dielectric material enables use of high-energy implants to form shallow doped regions. Other implanting steps may also be combined with the implanting through the dielectric material.

摘要翻译： 制造半导体器件的方法包括通过介电材料层执行掺杂注入。 通过介电材料的注入使得能够使用高能植入物形成浅掺杂区域。 其他植入步骤也可以与通过电介质材料的注入组合。

公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06764947B1

公开(公告)日：2004-07-20

申请号：US10366801

申请日：2003-02-14

申请人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

发明人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

IPC分类号： H01L214763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

摘要翻译： 在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。 应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。 应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。 在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

公开(公告)号：US06756255B1

公开(公告)日：2004-06-29

申请号：US10014064

申请日：2001-12-10

申请人： Ciby Thuruthiyil ,  Philip A. Fisher

发明人： Ciby Thuruthiyil ,  Philip A. Fisher

IPC分类号： H01L2182

CPC分类号： H01L27/0617 ,  H01L21/823842

摘要： A complementary metal oxide semiconductor (CMOS) fabrication process. The process comprises creating a polysilicon layer having a first thickness for a transistor gate area and a second thickness for a fuse area. The first thickness is greater than the second thickness, wherein most of the polysilicon in the fuse area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.

摘要翻译： 互补金属氧化物半导体（CMOS）制造工艺。 该工艺包括产生具有用于晶体管栅极区域的第一厚度和用于熔丝区域的第二厚度的多晶硅层。 第一厚度大于第二厚度，其中保险丝区域中的大多数多晶硅将在快速热退火（RTA）工艺期间与金属层反应以形成多硅化物。

公开(公告)号：US06747333B1

公开(公告)日：2004-06-08

申请号：US10274401

申请日：2002-10-18

申请人： Qi Xiang ,  Philip A. Fisher

发明人： Qi Xiang ,  Philip A. Fisher

IPC分类号： H01L2900

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A silicon-on-insulator semiconductor device, including a silicon-on-insulator wafer having a silicon active layer, a dielectric isolation layer a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate, in which the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer. The passivating insulator prevents formation of a bird's beak between the silicon active layer and the dielectric insulation layer during subsequent fabrication of the isolation trench.

摘要翻译： 一种绝缘体上半导体器件，包括具有硅有源层的绝缘体硅晶片，介质隔离层，硅衬底以及限定硅有源层中的有源岛的至少一个隔离沟槽，其中， 在绝缘层上形成硅有源层，并且在硅衬底上形成介电绝缘层，其中至少一个隔离沟槽在隔离沟槽的下部包括一层钝化绝缘体，并与该绝缘层接触 介电绝缘层。 钝化绝缘体防止在隔离沟槽的后续制造期间在硅有源层和介电绝缘层之间形成鸟嘴。

公开(公告)号：US06624300B2

公开(公告)日：2003-09-23

申请号：US09921846

申请日：2001-08-02

申请人： Richard C. Potter ,  Philip A. Fisher ,  Kirk R. Hash, Sr. ,  John D. Neidt

发明人： Richard C. Potter ,  Philip A. Fisher ,  Kirk R. Hash, Sr. ,  John D. Neidt

IPC分类号： C08B3700

CPC分类号： C08B37/0024 ,  C08B37/0003

摘要： An entirely aqueous method for concentrating beta-glucan from a beta-glucan source, such as milled cereal bran, grain or distiller's dried grain. The method comprises providing an alkaline aqueous extract of a beta-glucan source; acidifying or neutralizing the extract and heating the extract to between about 60° C. and 100° C.; cooling the extract, whereby a flocculate is formed; acidifying the cooled extract if the extract was neutralized; and removing the flocculate from the aqueous solution to form an intermediate solution. The intermediate solution may be subjected to ultrafiltration for further purification of beta-glucan, or may be evaporated, resulting in formation of a solid film enriched in beta-glucan. Beta-glucan has cholesterol-lowering properties and is a topical immunostimulant.

公开(公告)号：US20080090368A1

公开(公告)日：2008-04-17

申请号：US11580952

申请日：2006-10-16

申请人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

发明人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/31144 ,  H01L29/66659 ,  H01L29/66772

摘要： Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

摘要翻译： 提供了用于制造用于改善晶体管短沟道控制的突发和可调偏移间隔物的方法。 这些方法包括在电介质层内形成栅电极，仅露出栅电极的顶部。 例如，通过选择性外延生长将硅添加到栅电极的顶部。 介电层的蚀刻是在栅电极的顶部添加硅作为硅掩模进行的，以防止直接在硅掩模下面的电介质层的蚀刻，该掩模包括在栅电极侧壁上的突出端。 蚀刻以生产价值的方式产生偏移间隔物，并且可以用于形成不对称宽度的偏移间隔物。 通过在微加载方案中运行该方法，可以在较窄的多晶硅栅极特征上产生更宽的偏移间隔物，从而改善Vt滚降。

公开(公告)号：US20080070356A1

公开(公告)日：2008-03-20

申请号：US11520607

申请日：2006-09-14

申请人： Laura A. Brown ,  Philip A. Fisher ,  Huicai Zhong ,  Johannes Groschopf

发明人： Laura A. Brown ,  Philip A. Fisher ,  Huicai Zhong ,  Johannes Groschopf

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/41783 ,  H01L21/28114 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

摘要： The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the trench. A replacement gate is formed between the sidewall spacers and the sacrificial layer is removed to expose the raised source/drain regions. The sidewall spacers may then be removed from the sidewalls of the replacement gate, leaving the replacement gate a defined distance from the raised source/drain regions.

摘要翻译： 用于形成具有升高的源极/漏极的半导体器件布置的方法包括在衬底上沉积凸起的源极/漏极层，随后在凸起的源极/漏极层上沉积牺牲层。 在牺牲层和凸起的源极/漏极层中形成沟槽，并且在沟槽内形成侧壁间隔物。 在侧壁间隔件之间形成替换栅极，去除牺牲层以露出升高的源极/漏极区域。 然后可以从替换浇口的侧壁去除侧壁间隔物，使替换浇口与凸起的源极/漏极区域保持一定距离。

公开(公告)号：US07268066B2

公开(公告)日：2007-09-11

申请号：US10922093

申请日：2004-08-19

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/4763

CPC分类号： H01L29/66477 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。